4 MBIT (512KB X8 OR 256KB X16, BOOT BLOCK) SINGLE SUPPLY FLASH MEMORY

1/22

PRELIMINARY DATA

October 1999

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M29F400BT

M29F400BB

4 Mbit (512Kb x8 or 256Kb x16, Boot Block)

Single Supply Flash Memory

SINGLE 5V

10% SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPERATIONS

ACCESS TIME: 45ns

PROGRAMMING TIME

– 8

s per Byte/Word typical

11 MEMORY BLOCKS

– 1 Boot Block (Top or Bottom Location)

– 2 Parameter and 8 Main Blocks

PROGRAM/ERASE CONTROLLER

– Embedded Byte/Word Program algorithm

– Embedded Multi-Block/Chip Erase algorithm

– Status Register Polling and Toggle Bits

– Ready/Busy Output Pin

ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

TEMPORARY BLOCK UNPROTECTION

MODE

LOW POWER CONSUMPTION

– Standby and Automatic Standby

100,000 PROGRAM/ERASE CYCLES per

BLOCK

20 YEARS DATA RETENTION

– Defectivity below 1 ppm/year

ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h

– M29F400BT Device Code: 00D5h

– M29F400BB Device Code: 00D6h

TSOP48 (N)

12 x 20mm

SO44 (M)

Figure 1. Logic Diagram

AI02904

A0-A17

DQ0-DQ14

VCC

M29F400BT

M29F400BB

VSS

DQ15A–1

BYTE

M29F400BT, M29F400BB

2/22

Figure 2A. TSOP Connections

DQ3

DQ9

DQ2

DQ0

DQ6

DQ13

A17

A10

DQ14

DQ12

DQ10

DQ15A–1

VCC

DQ4

DQ5

DQ7

AI02905

M29F400BT

M29F400BB

DQ8

DQ1

DQ11

A12

A13

A16

A11

BYTE

A15

A14

VSS

Figure 2B. SO Connections

DQ0

DQ8

VSS

A13

VSS

A14

A15

DQ7

A12

A16

BYTE

DQ15A–1

DQ5

DQ2

DQ3

VCC

DQ11

DQ4

DQ14

AI02906

M29F400BT

M29F400BB

DQ1

DQ9

DQ6

DQ13

A11

A10

DQ10

DQ12

A17

Table 1. Signal Names

A0-A17

Address Inputs

DQ0-DQ7

Data Inputs/Outputs

DQ8-DQ14

Data Inputs/Outputs

DQ15A–1

Data Input/Output or Address Input

Chip Enable

Output Enable

Write Enable

Reset/Block Temporary Unprotect

Ready/Busy Output

BYTE

Byte/Word Organization Select

Supply Voltage

Ground

Not Connected Internally

SUMMARY DESCRIPTION

The M29F400B is a 4 Mbit (512Kb x8 or 256Kb

x16) non-volatile memory that can be read, erased

and reprogrammed. These operations can be per-

formed using a single 5V supply. On power-up the

memory defaults to its Read mode where it can be

read in the same way as a ROM or EPROM. The

M29F400B is fully backward compatible with the

M29F400.

The memory is divided into blocks that can be

erased independently so it is possible to preserve

valid data while old data is erased. Each block can

be protected independently to prevent accidental

Program or Erase commands from modifying the

memory. Program and Erase commands are writ-

ten to the Command Interface of the memory. An

on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by

taking care of all of the special operations that are

required to update the memory contents. The end

of a program or erase operation can be detected

and any error conditions identified. The command

set required to control the memory is consistent

with JEDEC standards.

3/22

M29F400BT, M29F400BB

The blocks in the memory are asymmetrically ar-

ranged, see Tables 3A and 3B, Block Addresses.

The first or last 64 Kbytes have been divided into

four additional blocks. The 16 Kbyte Boot Block

can be used for small initialization code to start the

microprocessor, the two 8 Kbyte Parameter

Blocks can be used for parameter storage and the

remaining 32K is a small Main Block where the ap-

plication may be stored.

Chip Enable, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The memory is offered in TSOP48 (12 x 20mm)

and SO44 packages. Access times of 45ns, 55ns,

70ns and 90ns are available. The memory is sup-

plied with all the bits erased (set to ’1’).

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diagram, and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A17). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation. During Bus

Write operations they represent the commands

sent to the Command Interface of the internal state

machine.

Data Inputs/Outputs (DQ8-DQ14). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation when BYTE

is High, V

. When BYTE is Low, V

, these pins

are not used and are high impedance. During Bus

Write operations the Command Register does not

use these bits. When reading the Status Register

these bits should be ignored.

Data Input/Output or Address Input (DQ15A-1).

When BYTE is High, V

, this pin behaves as a

Data Input/Output pin (as DQ8-DQ14). When

BYTE is Low, V

, this pin behaves as an address

pin; DQ15A–1 Low will select the LSB of the Word

on the other addresses, DQ15A–1 High will select

the MSB. Throughout the text consider references

to the Data Input/Output to include this pin when

BYTE is High and references to the Address In-

puts to include this pin when BYTE is Low except

when stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op-

erations to be performed. When Chip Enable is

High, V

, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

Symbol

Parameter

Value

Unit

Ambient Operating Temperature (Temperature Range Option 1)

0 to 70

Ambient Operating Temperature (Temperature Range Option 6)

–40 to 85

Ambient Operating Temperature (Temperature Range Option 3)

–40 to 125

BIAS

Temperature Under Bias

–50 to 125

STG

Storage Temperature

–65 to 150

(2)

Input or Output Voltage

–0.6 to 6

Supply Voltage

–0.6 to 6

Identification Voltage

–0.6 to 13.5

M29F400BT, M29F400BB

4/22

Table 3A. M29F400BT Block Addresses

Size

(Kbytes)

Address Range

(x8)

Address Range

(x16)

7C000h-7FFFFh

3E000h-3FFFFh

7A000h-7BFFFh

3D000h-3DFFFh

78000h-79FFFh

3C000h-3CFFFh

70000h-77FFFh

38000h-3BFFFh

60000h-6FFFFh

30000h-37FFFh

50000h-5FFFFh

28000h-2FFFFh

40000h-4FFFFh

20000h-27FFFh

30000h-3FFFFh

18000h-1FFFFh

20000h-2FFFFh

10000h-17FFFh

10000h-1FFFFh

08000h-0FFFFh

00000h-0FFFFh

00000h-07FFFh

Reset/Block Temporary Unprotect (RP). The Re-

set/Block Temporary Unprotect pin can be used to

apply a Hardware Reset to the memory or to tem-

porarily unprotect all Blocks that have been pro-

tected.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, V

, for at least

PLPX

. After Reset/Block Temporary Unprotect

goes High, V

, the memory will be ready for Bus

Read and Bus Write operations after t

PHEL

RHEL

, whichever occurs last. See the Ready/Busy

Output section, Table 14 and Figure 10, Reset/

Temporary Unprotect AC Characteristics for more

details.

Holding RP at V

will temporarily unprotect the

protected Blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from V

to V

must be slower than

PHPHH

Ready/Busy Output (RB). The Ready/Busy pin

is an open-drain output that can be used to identify

when the memory array can be read. Ready/Busy

is high-impedance during Read mode, Auto Select

mode and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes high-impedance. See Table 14 and Figure

10, Reset/Temporary Unprotect AC Characteris-

tics.

During Program or Erase operations Ready/Busy

is Low, V

. Ready/Busy will remain Low during

Table 3B. M29F400BB Block Addresses

Size

(Kbytes)

Address Range

(x8)

Address Range

(x16)

70000h-7FFFFh

38000h-3FFFFh

60000h-6FFFFh

30000h-37FFFh

50000h-5FFFFh

28000h-2FFFFh

40000h-4FFFFh

20000h-27FFFh

30000h-3FFFFh

18000h-1FFFFh

20000h-2FFFFh

10000h-17FFFh

10000h-1FFFFh

08000h-0FFFFh

04000h-07FFFh

06000h-07FFFh

03000h-03FFFh

04000h-05FFFh

02000h-02FFFh

00000h-03FFFh

00000h-01FFFh

Read/Reset commands or Hardware Resets until

the memory is ready to enter Read mode.

The use of an open-drain output allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then indicate

that one, or more, of the memories is busy.

Byte/Word Organization Select (BYTE). The Byte/

Word Organization Select pin is used to switch be-

tween the 8-bit and 16-bit Bus modes of the mem-

ory. When Byte/Word Organization Select is Low,

, the memory is in 8-bit mode, when it is High,

, the memory is in 16-bit mode.

Supply Voltage. The V

Supply Voltage

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

The Command Interface is disabled when the V

Supply Voltage is less than the Lockout Voltage,

LKO

. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being altered will be invalid.

A 0.1

F capacitor should be connected between

the V

Supply Voltage pin and the V

Ground

pin to decouple the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during program and

erase operations, I

CC4

Vss Ground. The V

Ground is the reference

for all voltage measurements.

5/22

M29F400BT, M29F400BB

Table 4A. Bus Operations, BYTE = V

Note: X = V

or V

Table 4B. Bus Operations, BYTE = V

Note: X = V

or V

Operation

Address Inputs

DQ15A–1, A0-A17

Data Inputs/Outpu ts

DQ14-DQ8

DQ7-DQ0

Bus Read

Cell Address

Hi-Z

Data Output

Bus Write

Command Address

Hi-Z

Data Input

Output Disable

Hi-Z

Standby

Hi-Z

Read Manufacturer

Code

A0 = V

, A1 = V

, A9 = V

Others V

or V

Hi-Z

20h

Read Device Code

A0 = V

, A1 = V

, A9 = V

Others V

or V

Hi-Z

D5h (M29F400BT)

D6h (M29F400BB)

Operation

Address Inputs

A0-A17

Data Inputs/Outpu ts

DQ15A–1, DQ14-DQ0

Bus Read

Cell Address

Data Output

Bus Write

Command Address

Data Input

Output Disable

Hi-Z

Standby

Hi-Z

Read Manufacturer

Code

A0 = V

, A1 = V

, A9 = V

Others V

or V

0020h

Read Device Code

A0 = V

, A1 = V

, A9 = V

Others V

or V

00D5h (M29F400BT)

00D6h (M29F400BB)

BUS OPERATIONS

There are five standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby and Automatic Standby. See

Tables 4A and 4B, Bus Operations, for a summa-

ry. Typically glitches of less than 5ns on Chip En-

able or Write Enable are ignored by the memory

and do not affect bus operations.

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desired address on the Address

Inputs, applying a Low signal, V

, to Chip Enable

and Output Enable and keeping Write Enable

High, V

. The Data Inputs/Outputs will output the

value, see Figure 7, Read Mode AC Waveforms,

and Table 11, Read AC Characteristics, for details

of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desired address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Data Inputs/Outputs are latched by the Com-

mand Interface on the rising edge of Chip Enable

or Write Enable, whichever occurs first. Output En-

able must remain High, V

, during the whole Bus

Write operation. See Figures 8 and 9, Write AC

Waveforms, and Tables 12 and 13, Write AC

Characteristics, for details of the timing require-

ments.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when Output Enable is

High, V

M29F400BT, M29F400BB

6/22

Standby. When Chip Enable is High, V

, the

Data Inputs/Outputs pins are placed in the high-

impedance state and the Supply Current is re-

duced to the Standby level.

When Chip Enable is at V

the Supply Current is

reduced to the TTL Standby Supply Current, I

CC2

To further reduce the Supply Current to the CMOS

Standby Supply Current, I

CC3

, Chip Enable should

be held within V

0.2V. For Standby current

levels see Table 10, DC Characteristics.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, I

CC4

, for Program or Erase operations un-

til the operation completes.

Automatic Standby. If CMOS levels (V

0.2V)

are used to drive the bus and the bus is inactive for

150ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

duced to the CMOS Standby Supply Current, I

CC3

The Data Inputs/Outputs will still output data if a

Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to

read the Electronic Signature and also to apply

and remove Block Protection. These bus opera-

tions are intended for use by programming equip-

ment and are not usually used in applications.

They require V

to be applied to some pins.

Electronic Signature. The

memory

has

two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These codes can be read by applying the signals

listed in Tables 4A and 4B, Bus Operations.

Block Protection and Blocks Unprotection. Each

block can be separately protected against acci-

dental Program or Erase. Protected blocks can be

unprotected to allow data to be changed.

There are two methods available for protecting

and unprotecting the blocks, one for use on pro-

gramming equipment and the other for in-system

use. For further information refer to Application

Note AN1122, Applying Protection and Unprotec-

tion to M29 Series Flash.

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. Failure to observe a valid sequence of Bus

Write operations will result in the memory return-

ing to Read mode. The long command sequences

are imposed to maximize data security.

The address used for the commands changes de-

pending on whether the memory is in 16-bit or 8-

bit mode. See either Table 5A, or 5B, depending

on the configuration that is being used, for a sum-

mary of the commands.

Read/Reset Command. The Read/Reset com-

mand returns the memory to its Read mode where

it behaves like a ROM or EPROM. It also resets

the errors in the Status Register. Either one or

three Bus Write operations can be used to issue

the Read/Reset command.

If the Read/Reset command is issued during a

Block Erase operation or following a Programming

or Erase error then the memory will take upto 10

to abort. During the abort period no valid data can

be read from the memory. Issuing a Read/Reset

command during a Block Erase operation will

leave invalid data in the memory.

Auto Select Command. The Auto Select com-

mand is used to read the Manufacturer Code, the

Device Code and the Block Protection Status.

Three consecutive Bus Write operations are re-

quired to issue the Auto Select command. Once

the Auto Select command is issued the memory

remains in Auto Select mode until another com-

mand is issued.

From the Auto Select mode the Manufacturer

Code can be read using a Bus Read operation

with A0 = V

and A1 = V

. The other address bits

may be set to either V

or V

. The Manufacturer

Code for STMicroelectronics is 0020h.

The Device Code can be read using a Bus Read

operation with A0 = V

and A1 = V

. The other

address bits may be set to either V

or V

. The

Device Code for the M29F400BT is 00D5h and for

the M29F400BB is 00D6h.

7/22

M29F400BT, M29F400BB

Table 5A. Commands, 16-bit mode, BYTE = V

Table 5B. Commands, 8-bit mode, BYTE = V

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.

All values in the table are in hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A17, DQ8-DQ14 and DQ15 are Don’t Care.

DQ15A–1 is A–1 when BYTE is V

or DQ15 when BYTE is V

Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.

Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.

Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase

Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Writ e

Operations until Timeout Bit is set.

Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.

Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.

Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands

on non-erasing blocks as normal.

Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/

Erase Controller completes and the memory returns to Read Mode.

Command

Length

Bus Write Operations

1st

2nd

3rd

4th

5th

6th

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read/Reset

555

2AA

Auto Select

555

2AA

555

Program

555

2AA

555

Unlock Bypass

555

2AA

555

Unlock Bypass

Program

Unlock Bypass Reset

Chip Erase

555

2AA

555

2AA

555

Block Erase

555

2AA

555

2AA

Erase Suspend

Erase Resume

Command

Length

Bus Write Operations

1st

2nd

3rd

4th

5th

6th

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read/Reset

AAA

555

Auto Select

AAA

555

AAA

Program

AAA

555

AAA

Unlock Bypass

AAA

555

AAA

Unlock Bypass

Program

Unlock Bypass Reset

Chip Erase

AAA

555