8-BIT MICROCONTROLLER (MCU) WITH OTP, ROM, FASTROM, EPROM, A/D CONVERTER, OSCILLATOR SAFEGUARD, SAFE RESET AND 16 PINS

August 1999

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Rev. 2.8

ST62T00C/T01C

ST62T03C/E01C

8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,

OSCILLATOR SAFEGUARD, SAFE RESET AND 16 PINS

3.0 to 6.0V Supply Operating Range

8 MHz Maximum Clock Frequency

-40 to +125

C Operating Temperature Range

Run, Wait and Stop Modes

5 Interrupt Vectors

Look-up Table capability in Program Memory

Data Storage in Program Memory:

User selectable size

Data RAM: 64bytes

User Programmable Options

9 I/O pins, fully programmable as:

– Input with pull-up resistor

– Input without pull-up resistor

– Input with interrupt generation

– Open-drain or push-pull output

– Analog Input (except ST62T03C)

3I/O lines can sink up to 20mA to drive LEDs or

TRIACs directly

8-bit Timer/Counter with 7-bit programmable

prescaler

Digital Watchdog

Oscillator Safe Guard

Low Voltage Detector for Safe Reset

8-bit A/D Converter with up to 4 analog inputs

On-chip Clock oscillator can be driven by Quartz

Crystal Ceramic resonator or RC network

Power-on Reset

One external Non-Maskable Interrupt

ST626x-EMU2 Emulation and Development

System (connects to an MS-DOS PC via a

parallel port)

DEVICE SUMMARY

DEVICE

OTP

(Bytes)

EPROM

(Bytes)

I/O Pins

Analog

inputs

ST62T00C

1036

ST62T01C

1836

ST62T03C

1036

None

ST62E01C

1836

(See end of Datasheet for Ordering Information)

PDIP16

PSO16

CDIP16W

SSOP16

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Table of Contents

Document

Page

ST62T00C/T01C/ST62T03C/E01C . . . . . . . . . . . . . . . . . . . . . . . 1

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.4.1 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.4.3 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 14

3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1.2 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1.3 Oscillator Safe Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.4 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.5 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.6 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.3.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.4.1 Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.4.4 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1.3 I/O Port Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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Table of Contents

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4.1.4 I/O Port Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1.5 I/O Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.2.1 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.2.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.2.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.3

A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.3.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

ST62P00C/P01C/P03C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

1.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

1.2.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

1.2.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

ST6200C/01C/03C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

1.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

1.3.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

1.3.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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ST62T00C/T01C ST62T03C/E01C

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST62T00C,T01C,T03C and ST62E01C de-

vices are low cost members of the ST62xx 8-bit

HCMOS family of microcontrollers, which is target-

ed at low to medium complexity applications. All

ST62xx devices are based on a building block ap-

proach: a common core is surrounded by a

number of on-chip peripherals.

The ST62E01C is the erasable EPROM version of

the ST62T00C,T01C,T03C and

device, which

may be used to emulate the ST62T00C,T01C and

T03C

device,

well

the

respective

ST6200C,01C and 03C ROM devices.

OTP and EPROM devices are functionally identi-

cal. The ROM based versions offer the same func-

tionality selecting as ROM options the options de-

fined in the programmable option bytes of the

OTP/EPROM versions.

OTP devices offer all the advantages of user pro-

grammability at low cost, which make them the

ideal choice in a wide range of applications where

frequent code changes, multiple code versions or

last minute programmability are required.

These compact low-cost devices feature a Timer

comprising an 8-bit counter and a 7-bit program-

mable prescaler,an 8-bit A/D Converter with up to

4 analog inputs and a Digital Watchdog timer,

making them well suited for a wide range of auto-

motive, appliance and industrial applications.

Figure 1. Block Diagram

TEST

NMI

INTERRUP T

PROGRAM

1836 Bytes

STACK LEVEL 1

STACK LEVEL 2

STACK LEVEL 3

STACK LEVEL 4

STACK LEVEL 5

STACK LEVEL 6

POWER

SUPPLY

OSCILLATOR

RESET

DATA ROM

USER

SELECTAB LE

DATA RAM

64 Bytes

PORT A

PORT B

TIMER

DIGITAL

8 BIT CORE

TEST/V

(ST62T01C, E01C)

8-BIT

A/D CONVERTER

PA1..PA 3 (20mA Sink)

OSCin OSCout

RESE T

WATCHDOG

MEMORY

PB0..PB1

1036 Bytes

(ST62T00C,T03C)

(*) Analog input availability depend on versions

PB3,PB5..PB 7 / Ain (*)

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ST62T00C/T01C ST62T03C/E01C

1.2 PIN DESCRIPTIONS

and V

. Power is supplied to the MCU via

these two pins. V

is the power connection and

is the ground connection.

OSCin and OSCout. These pins are internally

connected to the on-chip oscillator circuit. A quartz

crystal, a ceramic resonator or an external clock

signal can be connected between these two pins.

The OSCin pin is the input pin, the OSCout pin is

the output pin.

RESET. The active-low RESET pin is used to re-

start the microcontroller. Internal pull-up is provid-

ed at this pin.

TEST/V

. The TEST must be held at V

for nor-

mal operation. If TEST pin is connected to a

+12.5V level during the reset phase, the EPROM

programming Mode is entered.

NMI. The NMI pin provides the capability for asyn-

chronous interruption, by applying an external non

maskable interrupt to the MCU. The NMI input is

falling edge sensitive. The user can select as op-

tion the availability of an on-chip pull-up at this pin.

PA1-PA3. These 3 lines are organized as one I/O

port (A). Each line may be configured under soft-

ware control as inputs with or without internal pull-

up resistors, interrupt generating inputs with pull-

up resistors, open-drain or push-pull outputs. PA1-

PA3 can also sink 20mA for direct LED driving.

PB0..PB1,PB3,PB5-PB7. These 6 lines are or-

ganized as one I/O port (B). Each line may be con-

figured under software control as inputs with or

without internal pull-up resistors, interrupt generat-

ing inputs with pull-up resistors, open-drain or

push-pull outputs. PB3,PB5..-PB7 can be used as

analog inputs for the A/D converter on the

ST62T00C, T01C and E01C.

Figure 2. ST62T03C,T00C, T01C, and E01C Pin

Configuration

OSCin

OSCout

NMI

/TEST

RESET

Ain*/PB7

Ain*/PB6

PA1/20 mA Sink

PA2/20 mA Sink

PA3/20 mA Sink

PB0

PB1

PB3/Ain*

PB5/Ain*

*Analog input availability depend on device

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ST62T00C/T01C ST62T03C/E01C

MEMORY MAP (Cont’d)

1.3.2 Program Space

Program Space comprises the instructions to be

executed, the data required for immediate ad-

dressing mode instructions, the reserved factory

test area and the user vectors. Program Space is

addressed via the 12-bit Program Counter register

(PC register)Program Memory Protection.

The Program Memory in OTP or EPROM devices

can be protected against external readout of mem-

ory by selecting the READOUT PROTECTION op-

tion in the option byte.

In the EPROM parts, READOUT PROTECTION

option can be disactivated only by U.V. erasure

that also results into the whole EPROM context

erasure.

Note: Once the Readout Protection is activated, it

is no longer possible, even for STMicroelectronics,

to gain access to the OTP contents. Returned

parts with a protection set can therefore not be ac-

cepted.

Figure 4. Program Memory Map

(*) Reserved areas should be filled with 0FFh

0000h

0AFFh

0B00h

0B9Fh

NOT IMPLEMENTED

RESERVED

USER

PROGRAM MEMORY

(OTP)

1024 BYTES

0BA0h

0F9Fh

0FA0h

0FEFh

0FF0h

0FF7h

0FF8h

0FFBh

0FFCh

0FFDh

0FFEh

0FFFh

RESERVED

INTERRUPT VECTORS

NMI VECTOR

USER RESET VECTOR

0000h

07FFh

0800h

087Fh

NOT IMPLEMENTED

RESERVED

USER

PROGRAM MEMORY

(OTP/E PROM)

1824 BYTES

0880h

0F9Fh

0FA0h

0FEFh

0FF0h

0FF7h

0FF8h

0FFBh

0FFCh

0FFDh

0FFEh

0FFFh

RESERVED

INTERRUPT VECTORS

NMI VECTOR

USER RESET VECTOR

ST62T03C,T00C

ST62T01C, E01C

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ST62T00C/T01C ST62T03C/E01C

MEMORY MAP (Cont’d)

1.3.3 Data Space

Data Space accommodates all the data necessary

for processing the user program. This space com-

prises the RAM resource, the processor core and

peripheral registers, as well as read-only data

such as constants and look-up tables in OTP/

EPROM.

1.3.3.1 Data ROM

All read-only data is physically stored in program

memory, which also accommodates the Program

Space. The program memory consequently con-

tains the program code to be executed, as well as

the constants and look-up tables required by the

application.

The Data Space locations in which the different

constants and look-up tables are addressed by the

processor core may be thought of as a 64-byte

window through which it is possible to access the

read-only data stored in OTP/EPROM.

1.3.3.2 Data RAM

In ST6200C/01C/03C devices, the data space in-

cludes 60 bytes of RAM, the accumulator (A), the

indirect registers (X), (Y), the short direct registers

(V), (W), the I/O port registers, the peripheral data

and control registers, the interrupt option register

and the Data ROM Window register (DRW regis-

ter).

1.3.4 Stack Space

Stack space consists of six 12-bit registers which

are used to stack subroutine and interrupt return

addresses, as well as the current program counter

contents.

Table 1. ST6200C/01C/03C Data Memory Space

RESER VED

000h

03Fh

DATA ROM WINDOW AREA

64 BYTES

040h

07Fh

X REGISTER

080h

Y REGISTER

081h

V REGISTER

082h

W REGISTER

083h

DATA RAM 60 BYTES

084h

0BFh

PORT A DATA REGISTE R

0C0h

PORT B DATA REGISTE R

0C1h

RESER VED

0C2h

RESER VED

0C3h

PORT A DIRECTION REGISTE R

0C4h

PORT B DIRECTION REGISTE R

0C5h

RESER VED

0C6h

RESER VED

0C7h

INTERRUPT OPTION REGISTER

0C8h*

DATA ROM WINDOW REGISTER

0C9h*

RESER VED

0CAh

0CBh

PORT A OPTION REGISTER

0CCh

PORT B OPTION REGISTER

0CDh

RESER VED

0CEh

RESER VED

0CFh

A/D DATA REGIS TER(except ST62T03C)

0D0h

A/D CONTROL REGIS TER (except ST62T03C)

0D1h

TIMER PRESCALER REGISTER

0D2h

TIMER COUNTE R REGISTE R

0D3h

TIMER STATU S CONTRO L REGISTER

0D4h

RESER VED

0D5h

0D6h

0D7h

WATCH DOG REGISTER

0D8h

RESER VED

0D9h

0FEh

ACCUMULATOR

0FFh

* WRITE ONLY REGISTER

9/70

ST62T00C/T01C ST62T03C/E01C

MEMORY MAP (Cont’d)

1.3.5 Data Window Register (DWR)

The Data read-only memory window is located from

address 0040h to address 007Fh in Data space. It

allows direct reading of 64 consecutive bytes locat-

ed anywhere in program memory, between ad-

dress 0000h and 0FFFh (top memory address de-

pends on the specific device). All the program

memory can therefore be used to store either in-

structions or read-only data. Indeed, the window

can be moved in steps of 64 bytes along the pro-

gram memory by writing the appropriate code in the

Data Window Register (DWR).

The DWR can be addressed like any RAM location

in the Data Space, it is however a write-only regis-

ter and therefore cannot be accessed using single-

bit operations. This register is used to position the

64-byte read-only data window (from address 40h

to address 7Fh of the Data space) in program

memory in 64-byte steps. The effective address of

the byte to be read as data in program memory is

obtained by concatenating the 6 least significant

bits of the register address given in the instruction

(as least significant bits) and the content of the

DWR register (as most significant bits), as illustrat-

ed in Figure 5 below. For instance, when address-

ing location 0040h of the Data Space, with 0 load-

ed in the DWR register, the physical location ad-

dressed in program memory is 00h. The DWR reg-

ister is not cleared on reset, therefore it must be

written to prior to the first access to the Data read-

only memory window area.

Data Window Register (DWR)

Address: 0C9h

—

Write Only

Bits 6, 7 = Not used.

Bit 5-0 = DWR5-DWR0:

Data read-only memory

Window Register Bits. These are the Data read-

only memory Window bits that correspond to the

upper bits of the data read-only memory space.

Caution:

This register is undefined on reset. Nei-

ther read nor single bit instructions may be used to

address this register.

Note: Care is required when handling the DWR

DWR contents should not be changed while exe-

cuting an interrupt service routine, as the service

routine cannot save and then restore the register’s

previous contents. If it is impossible to avoid writ-

ing to the DWR during the interrupt service routine,

an image of the register must be saved in a RAM

location, and each time the program writes to the

DWR, it must also write to the image register. The

image register must be written first so that, if an in-

terrupt occurs between the two instructions, the

DWR is not affected.

Figure 5. Data read-only memory Window Memory Addressing

DWR5 DWR4 DWR3 DWR2 DWR1 DWR0

DATA ROM

WINDOW REGISTER

CONTENTS

DATA SPACE ADDRESS

40h-7Fh

IN INSTRUCTION

PROGRAM SPACE ADDRESS

READ

VR01573C

DATA SPACE ADDRESS

59h

Example:

(DWR)

DWR=28h

ROM

ADDRESS:A19h

10/70

ST62T00C/T01C ST62T03C/E01C

1.4 PROGRAMMING MODES

1.4.1 Option Bytes

The two Option Bytes allow configuration capabili-

ty to the MCUs. Option byte’s content is automati-

cally read, and the selected options enabled, when

the chip reset is activated.

It can only be accessed during the programming

mode. This access is made either automatically

(copy from a master device) or by selecting the

OPTION BYTE PROGRAMMING mode of the pro-

grammer.

The option bytes are located in a non-user map.

No address has to be specified.

EPROM Code Option Byte (LSB)

EPROM Code Option Byte (MSB)

D15-D11. Reserved. Must be cleared

D10. Reserved. Must be set to 1.

EXTCNTL.

External STOP MODE control.. When

EXTCNTL is high, STOP mode is available with

watchdog active by setting NMI pin to one.. When

EXTCNTL is low, STOP mode is not available with

the watchdog active.

LVD.

LVD RESET enable.When this bit is set, safe

RESET is performed by MCU when the supply

voltage is too low. When this bit is cleared, only

power-on reset or external RESET are active.

PROTECT.

Readout Protection. This bit allows the

protection of the software contents against piracy.

When the bit PROTECT is set high, readout of the

OTP contents is prevented by hardware.. When

this bit is low, the user program can be read.

OSCIL.

Oscillator selection. When this bit is low,

the oscillator must be controlled by a quartz crys-

tal, a ceramic resonator or an external frequency.

When it is high, the oscillator must be controlled by

an RC network, with only the resistor having to be

externally provided.

D5. Reserved. Must be cleared to zero.

D4. Reserved. Must be set to one.

NMI PULL.

NMI Pull-Up. This bit must be set high

to configure the NMI pin with a pull-up resistor.

When it is low, no pull-up is provided.

D2. Reserved. Must be set to 1.

WDACT. This bit controls the watchdog activation.

When it is high, hardware activation is selected.

The software activation is selected when WDACT

is low.

OSGEN.

Oscillator Safe Guard. This bit must be

set high to enable the Oscillator Safe Guard.

When this bit is low, the OSG is disabled.

The Option byte is written during programming ei-

ther by using the PC menu (PC driven Mode) or

automatically (stand-alone mode)

PRO-

TECT

OSCIL

NMI

PULL

WDACT

OS-

GEN

EXTC-

NTL

LVD

11/70

ST62T00C/T01C ST62T03C/E01C

PROGRAMMING MODES (Cont’d)

1.4.2 Program Memory

EPROM/OTP programming mode is set by a

+12.5V voltage applied to the TEST/V

pin. The

programming flow of the ST62T00C,T01C,T03C

and E01C is described in the User Manual of the

EPROM Programming Board.

Table 2. ST62T00C, T03C Program Memory Map

Table 3. ST62T01C,E01C Program Memory Map

Note: OTP/EPROM devices can be programmed

with the development tools available from STMi-

croelectronics (ST62E2X-EPB or ST622X-KIT).

1.4.3 EPROM Erasing

The EPROM of the windowed package of the

MCUs may be erased by exposure to Ultra Violet

light. The erasure characteristic of the MCUs is

such that erasure begins when the memory is ex-

posed to light with a wave lengths shorter than ap-

proximately 4000Å. It should be noted that sun-

lights and some types of fluorescent lamps have

wavelengths in the range 3000-4000Å.

It is thus recommended that the window of the

MCUs packages be covered by an opaque label to

prevent unintentional erasure problems when test-

ing the application in such an environment.

The recommended erasure procedure of the

MCUs EPROM is the exposure to short wave ul-

traviolet light which have a wave-length 2537A.

The integrated dose (i.e. U.V. intensity x exposure

time) for erasure should be a minimum of 30W-

sec/cm

. The erasure time with this dosage is ap-

proximately 30 to 40 minutes using an ultraviolet

lamp with 12000

W/cm

power rating. The

ST62E01C should be placed within 2.5cm (1Inch)

of the lamp tubes during erasure.

Device Address

Description

0000h-0B9Fh

0BA0h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h

0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFF h

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Device Address

Description

0000h-087Fh

0880h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h

0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFF h

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

12/70

ST62T00C/T01C ST62T03C/E01C

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

The CPU Core of ST6 devices is independent of the

I/O or Memory configuration. As such, it may be

thought of as an independent central processor

communicating with on-chip I/O, Memory and Pe-

ripherals via internal address, data, and control

buses. In-core communication is arranged as

shown in Figure 6; the controller being externally

linked to both the Reset and Oscillator circuits,

while the core is linked to the dedicated on-chip pe-

ripherals via the serial data bus and indirectly, for

interrupt purposes, through the control registers.

2.2 CPU REGISTERS

The ST6 Family CPU core features six registers and

three pairs of flags available to the programmer.

These are described in the following paragraphs.

Accumulator (A). The accumulator is an 8-bit

general purpose register used in all arithmetic cal-

culations, logical operations, and data manipula-

tions. The accumulator can be addressed in Data

space as a RAM location at address FFh. Thus the

ST6 can manipulate the accumulator just like any

other register in Data space.

Indirect Registers (X, Y). These two indirect reg-

isters are used as pointers to memory locations in

Data space. They are used in the register-indirect

addressing mode. These registers can be ad-

dressed in the data space as RAM locations at ad-

dresses 80h (X) and 81h (Y). They can also be ac-

cessed with the direct, short direct, or bit direct ad-

dressing modes. Accordingly, the ST6 instruction

set can use the indirect registers as any other reg-

ister of the data space.

Short Direct Registers (V, W). These two regis-

ters are used to save a byte in short direct ad-

dressing mode. They can be addressed in Data

space as RAM locations at addresses 82h (V) and

83h (W). They can also be accessed using the di-

rect and bit direct addressing modes. Thus, the

ST6 instruction set can use the short direct regis-

ters as any other register of the data space.

Program Counter (PC). The program counter is a

12-bit register which contains the address of the

next ROM location to be processed by the core.

This ROM location may be an opcode, an oper-

and, or the address of an operand. The 12-bit

length allows the direct addressing of 4096 bytes

in Program space.

Figure 6. ST6 Core Block Diagram

PROGRAM

RESET

OPCODE

FLAG

VALUES

CONTR OLLER

FLAGS

ALU

A-DATA

B-DATA

ADDRESS /READ LINE

DATA SPACE

INTERRUPTS

DATA

RAM/EEPR OM

DATA

ROM/EPRO M

RESULTS TO DATA SPACE (WRITE LINE)

ROM/EPROM

DEDICAT IONS

ACCUMULATOR

CONTROL

SIGNALS

OSCin

OSCout

ADDRESS

DECODER

256

Program Counter

and

6 LAYER STACK

0,01 TO 8MHz

VR01811