DATA SHEET
Preliminary specification
File under Integrated Circuits, IC02
February 1995
INTEGRATED CIRCUITS
Philips Semiconductors
SAA5290
One page Economy Teletext/TV
microcontroller
February 1995
2
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV
microcontroller
SAA5290
FEATURES
General
•
Complete one page teletext decoder and TV
microcontroller in a single 52-pin package
•
Eastern European, Western European and Turkish
language variants covered in one device
•
Double size, double width and double height character
capability for On-Screen Display (OSD)
•
Enhanced display features including meshing and
shadowing
•
Separate display and acquisition timing for increased
flexibility
•
Minimum peripheral component count
•
525 line and 625 line display synchronization
•
Standby mode through power-down of teletext and
analog hardware.
Microcontroller
•
16 kbytes masked ROM (16 kbytes EEPROM variant for
product development)
•
256 bytes of on-chip RAM
•
Six 6-bit Pulse Width Modulators (PWM) and one 14-bit
precision PWM
•
4-bit Digital-to-Analog Converter (DAC) and comparator
with a 3-input multiplexer allowing implementation of 3
Analog-to-Digital Converters (ADC) in software
•
2 high current (10 mA) open-drain outputs
•
Interrupt logic 0 triggered on rising and falling edges,
providing pulse-width measurement for remote control
decoding
•
Master and slave bit-level I
2
C-bus hardware.
DESCRIPTION
The SAA5290 is a single-chip one page teletext decoder
and television control microcontroller. The device will
decode 625-line based World System Teletext
transmissions and provides television control functions
and On-Screen Display (OSD) functions.
The teletext decoder hardware is a derivative of the
SAA5254 (IVT1.1X), and the TV control functionality
provided by an on-chip industrial standard 80C51
microcontroller. A single-page static RAM is included
on-board providing a complete one page teletext decoder
and OSD memory.
The SAA5290 is available as a mask-programmed ROM
version. An EEPROM version is also available for product
development. Both versions are available in an SDIP52
package.
ORDERING INFORMATION
Notes
1. nnn is a three-digit number referencing the microcontroller program ROM mask.
2. I is a digit number referring to the language variant of the SAA5290ZP/NV.
TYPE NUMBER
MEMORY
PACKAGE
NAME
DESCRIPTION
VERSION
SAA5290ZP/nnn
(1)
ROM
SDIP52
plastic shrink dual in-line package; 52 leads (600 mil)
SOT247-1
SAA5290ZP/NVI
(2)
EEPROM
SDIP52
plastic shrink dual in-line package; 52 leads (600 mil)
SOT247-1
February 1995
3
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV
microcontroller
SAA5290
QUICK REFERENCE DATA
BLOCK DIAGRAM
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
V
DD
supply voltage
4.5
5.0
5.5
V
I
DDM
microcontroller supply current
−
25
40
mA
I
DDA
analog supply current
−
35
50
mA
I
DDT
teletext supply current
−
20
30
mA
f
xtal
crystal frequency
−
12
−
MHz
T
amb
operating ambient temperature
−
20
−
+70
°
C
Fig.1 Block diagram.
handbook, full pagewidth
MLC102
DATA SLICER
ACQUISITION
TIMING
TELETEXT
ACQUISITION
DISPLAY
TIMING
DISPLAY
PAGE
RAM
OSCILLATOR
80C51
MICRO-
CONTROLLER
ANALOG-TO-
DIGITAL
CONVERTER
PULSE
WIDTH
MODULATOR
TIMER/
CTRS/ I C
2
data
address
16K x 8
ROM
PORT 3
9 to 12, 30
5
256 x 8
RAM
PORT 2
1 to 8
8
TEXT
INTERFACE
PORT 1
45 to 52
8
PORT 0
14 to 21
8
P3.0 to P3.4/
ADC0 to ADC2
P2.0 to P2.7
PWM
P1.0 to P1.7 / INT0,
INT1, T0, T1, SDA, SCL
P0.0 to P0.7
VSSA
22
VSSD2
VSSD1
28
13
43
RESET
40
OSCGND
42
OSCOUT
41
OSCIN
SAA5290
37
VSYNC
36
HSYNC
27
FRAME
RGBREF
34, 33, 32
R, G, B
35
31
VDS
29
COR
25
26
BLACK
IREF
CVBS0
CVBS1
23, 24
2
38
39
44
VDDM
VDDT
VDDA
3
February 1995
4
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV
microcontroller
SAA5290
PINNING
SYMBOL
PIN
DESCRIPTION
P2.0/TPWM
1
PORT 2: 8-bit open-drain bidirectional port with alternative functions. P2.0/TPWM is the
output for the 14-bit high precision PWM. P2.1/PWM0 to P2.6/PWM5 are the outputs for
the 6-bit PWMs 0 to 5.
P2.1/PWM0
2
P2.2/PWM1
3
P2.3/PWM2
4
P2.4/PWM3
5
P2.5/PWM4
6
P2.6/PWM5
7
P2.7
8
P3.0/ADC0
9
PORT 3: 5-bit open-drain bidirectional port with alternative functions. P3.0/ADC0 to
P3.2/ADC2 are the inputs for the software ADC facility.
P3.1/ADC1
10
P3.2/ADC2
11
P3.3
12
P3.4
30
V
SSD1
13
digital ground 1 for teletext and microcontroller circuits.
P0.0
14
PORT 0: 8-bit open-drain bidirectional port. P0.5 and P0.6 have 10 mA current sinking
capability at 0.5 V for direct drive of LEDs.
P0.1
15
P0.2
16
P0.3
17
P0.4
18
P0.5
19
P0.6
20
P0.7
21
V
SSA
22
analog ground.
CVBS0
23
Composite video input. A positive-going 1 V (peak-to-peak) input is required, connected
via a 100 nF capacitor.
CVBS1
24
BLACK
25
Video black level storage input. This pin should be connected to V
SSA
via a 100 nF
capacitor.
IREF
26
Reference current input for analog circuits, connected to V
SSA
via a 27 k
Ω
resistor.
FRAME
27
De-interlace output synchronized with the VSYNC pulse to produce a non-interlaced
display by adjustment of the vertical deflection currents.
V
SSD2
28
Digital ground 2.
COR
29
Open-drain, active LOW output which allows selective contrast reduction of the TV
picture to enhance a mixed mode display.
RGBREF
31
DC input voltage to define the output HIGH level on the RGB pins.
B
32
Dot rate character output of the BLUE colour information.
G
33
Dot rate character output of the GREEN colour information.
R
34
Dot rate character output of the RED colour information.
VDS
35
Video/data switch push-pull output for dot rate fast blanking.
HSYNC
36
Horizontal sync dedicated input for a TTL-level version of the horizontal sync pulse. The
polarity of this pulse is programmable by register bit TXT1.H POLARITY.
February 1995
5
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV
microcontroller
SAA5290
VSYNC
37
Vertical sync dedicated input for a TTL-level version of the vertical sync pulse. The
polarity of this pulse is programmable by register bit TXT1.V POLARITY.
V
DDA
38
+5 V analog power supply.
V
DDT
39
+5 V teletext power supply.
OSCGND
40
Crystal oscillator ground.
OSCIN
41
12 MHz crystal oscillator input.
OSCOUT
42
12 MHz crystal oscillator output.
RESET
43
If the reset input is HIGH for 2 machine cycles (24 oscillator periods) while the oscillator
is running, the SAA5290 is reset. This pin should be connected to V
DDM
via a 2.2
µ
F
capacitor.
V
DDM
44
+5 V microcontroller power supply.
P1.0/INT1
45
PORT 1: 8-bit open-drain bidirectional port with alternative functions. P1.0/INT1 is
external interrupt 1 which can be triggered on the rising and falling edge of the pulse.
P1.1/T0 is the counter/timer 0. P1.2/INT0 is external interrupt 0. P1.3/T1 is the
counter/timer 1. P1.6/SCL is the serial clock input for I
2
C-bus. P1.7/SDA is the serial
data port for the I
2
C-bus.
P1.1/T0
46
P1.2/INT0
47
P1.3/T1
48
P1.6/SCL
49
P1.7/SDA
50
P1.4
51
P1.5
52
SYMBOL
PIN
DESCRIPTION
February 1995
6
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV
microcontroller
SAA5290
Fig.2 Pin configuration.
handbook, halfpage
1
2
3
4
5
6
7
8
9
10
11
12
13
40
39
38
37
36
35
34
33
32
31
30
29
28
27
14
15
16
17
18
19
20
22
23
24
25
26
21
42
41
43
44
45
46
47
48
49
50
51
52
MLC103
SAA5290
P2.0/TPWM
P2.1/PWM0
P2.2/PWM1
P2.3/PWM2
P2.4/PWM3
P2.5/PWM4
P2.6/PWM5
P2.7
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
CVBS0
CVBS1
BLACK
IREF
SSD1
V
DDM
V
DDT
V
DDA
V
SSD2
V
SSA
V
P1.5
P1.4
P1.7/SDA
P1.6/SCL
P1.3/T1
P1.2/INT0
P1.1/T0
P1.0/INT1
RESET
OSCOUT
OSCIN
OSCGND
VSYNC
HSYNC
VDS
R
G
B
RGBREF
P3.4
COR
FRAME
February 1995
7
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV
microcontroller
SAA5290
QUALITY AND RELIABILITY
This device will meet Philips Semiconductors General Quality Specification for Business group
“Consumer Integrated
Circuits SNW-FQ-611-Part E” (see “Quality Reference Handbook”, order number 9398 510 63011). The principal
requirements are shown in Tables 1 to 4.
Group A
Table 1 Acceptance tests per lot
Group B
Table 2 Processability tests (by package family)
Group C
Table 3 Reliability tests (by process family)
Table 4 Reliability tests (by device type)
Notes to Tables 1 to 4
1. ppm = fraction of defective devices, in parts per million.
LTPD = Lot Tolerance Percent Defective.
FPM = fraction of devices failing at test condition, in Failures Per Million.
FITS = Failures In Time Standard.
TEST
REQUIREMENTS
(1)
Mechanical
cumulative target:
<
80 ppm
Electrical
cumulative target:
<
80 ppm
TEST
REQUIREMENTS
(1)
Solderability
<
7% LTPD
Mechanical
<
15% LTPD
Solder heat resistance
<
15% LTPD
TEST
CONDITIONS
REQUIREMENTS
(1)
Operational life
168 hours at T
j
= 150
°
C
<
1500 FPM; equivalent to
<
100 FITS at T
j
= 70
°
C
Humidity life
temperature, humidity, bias
1000 hours, 85
°
C, 85% RH
(or equivalent test)
<
2000 FPM
Temperature cycling performance
T
stg(min)
to T
stg(max)
<
2000 FPM
TEST
CONDITIONS
REQUIREMENTS
(1)
ESD and latch-up
ESD Human body model
2000 V, 100 pF, 1.5 k
Ω
<
15% LTPD
ESD Machine model
200 V, 200 pF, 0
Ω
<
15% LTPD
latch-up 100 mA, 1.5
×
V
DD
(absolute maximum)
<
15% LTPD
February 1995
8
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV
microcontroller
SAA5290
LIMITING VALUES
In accordance with Absolute Maximum Rating System (IEC 134).
Notes
1. This maximum value has an absolute maximum of 6.5 V independent of V
DD
.
2. Except in standby mode.
CHARACTERISTICS
V
DD
= 5 V
±
10%; V
SS
= 0 V; T
amb
=
−
20 to +70
°
C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DD
supply voltage (all supplies)
−
0.3
+6.5
V
V
I
input voltage (any input)
note 1
−
0.3
V
DD
+ 0.5 V
V
O
output voltage (any output)
note 1
−
0.3
V
DD
+ 0.5 V
I
O
output current (each output)
−
±
10
mA
I
IOK
DC input or output diode current
−
±
20
mA
∆
V
SS
difference between V
SSD
, V
SSA
and OSCGND
−
±
0.1
V
∆
V
DD
difference between V
DDM
, V
DDT
and V
DDA
note 2
−
±
0.1
V
T
amb
operating ambient temperature
−
20
+70
°
C
T
stg
storage temperature
−
55
+125
°
C
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
DD
supply voltage (V
DD
to V
SS
)
4.5
5.0
5.5
V
I
DDM
microcontroller supply current
−
25
40
mA
I
DDA
analog supply current
−
35
50
mA
I
DDT
teletext supply current
−
20
30
mA
Digital inputs
RESET
V
IL
LOW level input voltage
−
0.3
−
0.2V
DD
−
0.1 V
V
IH
HIGH level input voltage
0.7V
DD
−
V
DD
+ 0.3
V
I
LI
input leakage current
V
I
= 0 to V
DD
−
10
−
+10
µ
A
C
I
input capacitance
−
−
4
pF
HSYNC
AND
VSYNC
V
thf
switching threshold falling
0.2V
DD
−
−
V
V
thr
switching threshold rising
−
−
0.8V
DD
V
V
HYS
hysteresis voltage
−
0.33V
DD
−
V
C
I
input capacitance
−
−
4
pF
February 1995
9
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV
microcontroller
SAA5290
Digital outputs
R, G
AND
B (note 1)
V
OL
LOW level output voltage
I
OL
= 2 mA
0
−
0.2
V
V
OH
HIGH level output voltage
I
OH
=
−
2 mA
V
RGBREF
−
0.3
V
RGBREF
V
RGBREF
+ 0.4
V
|
Z
O
|
output impedance
−
−
150
Ω
C
L
load capacitance
−
−
50
pF
I
O
DC output current
−
−
−
4
mA
t
r
output rise time
between 10% and 90%;
C
L
= 50 pF
−
−
20
ns
t
f
output fall time
between 90% and 10%;
C
L
= 50 pF
−
−
20
ns
COR (
OPEN
-
DRAIN OUTPUT
)
V
OH
HIGH level pull-up output
voltage
−
−
V
DD
V
V
OL
LOW level output voltage
I
OL
= 2 mA
0
−
0.5
V
I
OL
LOW level output current
−
−
2
mA
C
L
load capacitance
−
−
25
pF
VDS
V
OL
LOW level output voltage
I
OL
= 1.6 mA
0
−
0.2
V
V
OH
HIGH level output voltage
I
OH
=
−
1.6 mA
V
DD
−
0.3
−
V
DD
+ 0.4
V
C
L
load capacitance
−
−
50
pF
t
r
output rise time
between 10% and 90%;
C
L
= 50 pF
−
−
20
ns
t
f
output fall time
between 90% and 10%;
C
L
= 50 pF
−
−
20
ns
R, G, B
AND
VDS
t
skew
skew delay between any two
pins
−
−
20
ns
FRAME
V
OH
HIGH level output voltage
I
OL
= 8 mA
0
−
0.5
V
V
OL
LOW level output voltage
I
OL
=
−
8 mA
V
DD
−
0.5
−
V
DD
V
I
OL
LOW level output current
−
8
−
+8
mA
C
L
load capacitance
−
−
100
pF
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
February 1995
10
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV
microcontroller
SAA5290
Digital input/outputs
P0.0
TO
P0.4, P0.7, P1.0
TO
P1.5, P2.0
TO
P2.7
AND
P3.0
TO
P3.5
V
IL
LOW level input voltage
−
0.3
−
0.2V
DD
−
0.1 V
V
IH
HIGH level input voltage
0.2V
DD
+ 0.9
−
V
DD
+ 0.3
V
C
I
input capacitance
−
−
4
pF
V
OL
LOW level output voltage
I
OL
= 3.2 mA
0
−
0.45
V
C
L
load capacitance
−
−
50
pF
P0.5
AND
P0.6
V
IL
LOW level input voltage
−
0.3
−
0.2V
DD
−
0.1 V
V
IH
HIGH level input voltage
0.2V
DD
+ 0.9
−
V
DD
+ 0.3
V
C
I
input capacitance
−