DATA SHEET
Objective specification
File under Integrated Circuits, IC01
1996 Jun 17
INTEGRATED CIRCUITS
SAA7367
Bitstream conversion ADC for
digital audio systems
1996 Jun 17
2
Philips Semiconductors
Objective specification
Bitstream conversion ADC for
digital audio systems
SAA7367
FEATURES
•
Total Harmonic Distortion plus Noise
(THD + N) =
−
88 dB (0.004%); DR = 93 dB;
S/N = 97 dB
•
Simple interfacing to analog inputs
•
Small, non-critical PCB layout
•
Low pin-out SO24 package (pin-compatible to
SAA7366)
•
4 flexible serial interface modes
•
4.5 to 5.5 V operation
•
Standby mode
•
Detection of digital signal
≥−
1 dB amplitude
•
Up to 18 significant bits serial output
•
Selectable high-pass filter.
APPLICATIONS
The device is designed for the digital acquisition of analog
audio signals for digital audio systems such as:
•
Compact Disc-Recordable (CD-R)
•
Digital Compact Cassette (DCC)
•
Digital Audio Tape (DAT).
GENERAL DESCRIPTION
The SAA7367 is a CMOS low-cost stereo
Analog-to-Digital Converter (ADC) using the Philips
bitstream conversion technique.
QUICK REFERENCE DATA
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DDD
digital supply voltage
4.5
5.0
5.5
V
I
DDD
digital supply current
−
17
−
mA
V
DDA
analog supply voltage
4.5
5.0
5.5
V
I
DDA
analog supply current
−
13
−
mA
f
BCK
clock input frequency
4.60
12.288
12.8
MHz
f
s
sample rate
18
48
50
kHz
THD + N
total harmonic distortion plus
noise
at 0 dB input
−
−
88
−
80
dB
DR
dynamic range
at
−
60 dB
90
93
−
dB
S/N
signal-to-noise ratio
−
97
−
dB
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
SAA7367
SO24
plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
1996 Jun 17
3
Philips Semiconductors
Objective specification
Bitstream conversion ADC for
digital audio systems
SAA7367
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
MGE645
SAA7367
REFERENCE
VOLTAGE
GENERATOR
CLOCK
GENERATION
AND
CONTROL
SIGMA-
DELTA
MODULATOR
REFERENCE
CURRENT
GENERATOR
TIMING
GENERATOR
DECIMATION FILTER
STAGE 1
COMB
FILTER
STAGE 2
3 HALF-BAND
FILTERS
HIGH-PASS
FILTER
SERIAL OUTPUT
INTERFACE
SIGMA-
DELTA
MODULATOR
REFERENCE
VOLTAGE
GENERATOR
operational
amplifier
operational
amplifier
operational
amplifier
operational
amplifier
16
17
19
14
18
20
21
22
23
11
1
9
8
7
6
5
4
2
12
15
13
SFOR
STDB
3
OVLD
VDDD
VSSD
CKIN
SDO
SWS
SCK
HPEN
TESTB
VrefR
VSSA
24
SLAVE
10
TEST1
BOR
BOL
BIL
Iref
BIR
VDACP
VDACN
VDDA
VrefL
1996 Jun 17
4
Philips Semiconductors
Objective specification
Bitstream conversion ADC for
digital audio systems
SAA7367
PINNING
SYMBOL
PIN
DESCRIPTION
SFOR
1
TTL level input; in normal mode this input selects the serial interface output format; output
format is selected as follows:
SFOR = HIGH selects Format 1
SFOR = LOW selects Format 2 (similar to I
2
S)
STDB
2
schmitt-trigger input; in normal mode, this input is used to select standby mode:
STDB = HIGH selects normal operation
STDB = LOW selects standby mode (low power consumption)
OVLD
3
TTL level output; in normal mode this output indicates whether the internal digital signal is
within 1 dB of maximum; if so, the output will go HIGH for 131072 clock cycles (approximately
11 ms); in standby mode this output is forced LOW
CKIN
4
CMOS level input; system clock input; nominally clocked at 256f
s
V
DDD
5
digital supply voltage (4.5 to 5.5 V)
V
SSD
6
digital ground
SDO
7
TTL level output (3-state); in normal mode this pin outputs data from the serial interface; in
standby mode, this output is high impedance
SWS
8
TTL level input/output; serial interface word select signal; in master mode (SLAVE = LOW),
this pin outputs the serial interface word select signal; in slave mode (SLAVE = HIGH), this pin
is the word select input to the serial interface; in standby mode (STDB = LOW) this pin is
always an input (high impedance); for polarity: see Table 1
SCK
9
TTL level input/output; in master mode (SLAVE = LOW) the pin outputs the serial interface bit
clock; in slave mode (SLAVE = HIGH) this pin is the input for the external bit clock; data on
SDO is clocked out on the HIGH-to-LOW transition of SCK; the data is valid on the
LOW-to-HIGH transition
TEST1
10
Test 1; TTL level input with internal pull-down; in slave mode (slave = HIGH), this pin is used
to select extra serial interface formats (see Table 2)
HPEN
11
TTL level input; this input is used to enable the internal high-pass filter when HIGH; in
scan-test mode (TESTB = LOW and TEST1 = LOW) this pin functions as ‘scan chain c’ input
TESTB
12
Test B; CMOS level input with internal pull-up; in normal applications, this input should be left
HIGH
V
SSA
13
analog ground; this pin is internally connected to V
SS
via the on-chip substrate contacts
I
ref
14
current reference generator output; 33 k
Ω
in parallel with 22 nF is connected from this pin to
V
SSA
V
refR
15
right channel analog reference output voltage (
1
⁄
2
V
DDA
)
BIR
16
buffer operational amplifier inverting input for right channel
BOR
17
buffer operational amplifier output for right channel
V
DACN
18
negative 1-bit DAC reference voltage input, connected to 0 V
V
DACP
19
positive 1-bit DAC reference voltage input, connected to +5 V
BOL
20
buffer operational amplifier output for left channel
BIL
21
buffer operational amplifier inverting input for left channel
V
refL
22
left channel analog reference output voltage (
1
⁄
2
V
DDA
)
V
DDA
23
analog supply voltage (4.5 to 5.5 V)
1996 Jun 17
5
Philips Semiconductors
Objective specification
Bitstream conversion ADC for
digital audio systems
SAA7367
Table 1
SWS polarity
Table 2
Selection of serial interface formats via TEST1
SLAVE
24
TTL level input; used to select the serial interface operating mode:
SLAVE = HIGH selects slave mode
SLAVE = LOW selects master mode
CONDITIONS
POLARITY
SLAVE AND TEST1
SWS
SFOR
SLAVE = LOW or TEST1 = LOW
LOW
LOW
left data
LOW
HIGH
right data
SLAVE = HIGH and TEST1 = HIGH
LOW
LOW
right data
LOW
HIGH
left data
CONDITIONS
SELECTED FORMAT
SFOR
TEST1
HIGH
LOW
format 1
HIGH
format 2
LOW
LOW
format 3
HIGH
format 4
SYMBOL
PIN
DESCRIPTION
Fig.2 Pin configuration.
handbook, halfpage
SFOR
STDB
OVLD
CKIN
VDDD
VSSD
SDO
SWS
SCK
TEST1
HPEN
TESTB
SLAVE
VDDA
VrefL
BIL
VDACP
VDACN
BOL
BOR
BIR
VrefR
Iref
VSSA
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SAA7367
MGE644
FUNCTIONAL DESCRIPTION
General
The SAA7367 is a bitstream conversion CMOS ADC for
digital audio systems. The conversion is achieved using a
third-order Sigma-Delta Modulator (SDM), running at
128 times the output sample frequency (f
s
). The high
oversampling ratio greatly simplifies the design of the
analog input anti-alias filter. In most events, the internal
buffer operational amplifier, configured as a low-pass filter,
will suffice. The 1-bit code from the SDM is filtered and
down-sampled (decimated) to 1f
s
by Finite Impulse
Response (FIR) filters. An optional I
2
R high-pass filter is
provided to remove DC, if required. The device has been
designed with ease of use, low board area and low
application costs in mind.
Clock frequency
The external clock input on pin CKIN runs at 256f
s
, which
can range from 18 to 50 kHz.
1996 Jun 17
6
Philips Semiconductors
Objective specification
Bitstream conversion ADC for
digital audio systems
SAA7367
Input buffer
Two input buffers are provided, one for each channel, for
signal amplitude matching, signal buffering and anti-alias
filter purposes. These are configured for inverting use.
Access is provided by pins BIL, BIR (inverting inputs) and
BOL, BOR (outputs), for left and right channels
respectively. By the choice of feedback component values,
the application signal amplitude can be matched to the
requirements of the ADC.
Typically, the operational amplifiers are configured as
low-pass filters with a gain of 1 and a pole at
approximately 5f
s
.
Remark: the complete ADC is non-inverting. Hence, a
positive DC input (referenced to V
ref
) will yield a positive
digital output.
Input level
The overall system gain is proportional V
DDA
, or more
accurately the potential difference between the DAC
reference voltages (V
VDACP
) and (V
VDACN
). For
convenience, the ADC input signal amplitude is defined as
that amplitude seen on BOL or BOR, the operational
amplifier outputs (i.e. the input to the SDM). Also, the 0 dB
input level is defined as that which gives a
−
1 dB (actually
−
1.12 dB) digital output, relative to full-scale swing. This
reduced gain provides headroom to accommodate small
random DC offsets, without causing the digital output to
clip.
Hence:
The user of the IC should ensure that, when all sources of
signal amplitude variation are taken into account, the
maximum input signal should conform to the 0 dB level.
In the event that the maximum signal level cannot be
pre-determined, e.g. live microphone input, the average
signal level should be set at
−
10 to
−
20 dB down. The
exact value will depend on the application and the balance
between headroom and operating Signal-to-Noise Ratio
(SNR).
Behaviour during overload
As previously defined, the maximum input level for normal
operation is 0 dB. If the input level exceeds this value,
clipping may occur. Within the system, excessive
amplitudes are detected after the high-pass filter.
Infringements are limited to the maximum permitted
positive or negative values 2
17
−
1 or
−
2
17
respectively.
V
I
0 dB
(
)
V
VDACP
V
VDACN
–
(
)
5 V (RMS)
-------------------------------------------------------
=
Input signals in the range 0 to 1 dB may or may not be
clipped, depending on the values of DC dither and small
random offsets in the analog circuitry.
When using the recommended application circuitry,
clipping will initially be observed on negative peaks, due to
the use of negative DC dither.
The maximum level of overload that can be safely
tolerated is application circuit dependent. In the case of the
recommended circuit, the following applies: the inverting
operational amplifier inputs BIL and BIR are protected
from excessive voltages (currents) by diodes to V
DDA
and
V
SSA
. These have absolute maximum ratings of
I
d
=
±
20 mA, with a safe practical limit of
±
2 mA.
Given the input resistor of 10 k
Ω
,
±
2 mA diode current and
the operation of the operational amplifier, a maximum
signal (applied to the input resistor) of
±
30 V can be
handled safely. This level represents an overload of 26 dB.
During overload, the in-band portion of the waveform will
be correctly converted. The out-of-band portion will be
limited as previously detailed.
Sigma-Delta Modulator (SDM)
The SAA7367 uses two third-order SDMs with a
quantization noise floor of approximately
−
104 dB. The
scaling of the feedback has been optimized for stable
operation, even during overload. Thus, with a maximum
signal swing of 0 V to V
DDA
on the input, the digital output
remains well-behaved, i.e. it does not burst into random
oscillation. During overload, the output is simply a clipped
version of the input. The gain of this stage is
−
4.64 dB.
Decimation filter
Decimation from 128f
s
is performed in two stages. The first
stage, a comb filter, uses 64 symmetrical coefficients to
implement a 3rd sin
x
⁄
x
characteristic. This filter decimates
from 128 to 8f
s
. The second stage, an FIR filter, consists of
three half-band filters, each decimating by a factor of 2.
The overall characteristics are given in Table 3.
1996 Jun 17
7
Philips Semiconductors
Objective specification
Bitstream conversion ADC for
digital audio systems
SAA7367
Table 3
Overall filter characteristics
High-pass filter
An optional I
2
R high-pass filter is provided to remove
unwanted DC components. The operation is selected
when HPEN is HIGH and deselected when LOW. The filter
has the characteristics given in Table 4.
Table 4
High-pass filter characteristics
Serial interface
The serial interface provides 2 formats in master mode
and 4 in slave mode (see Figs 3 and 4). Format 2 is similar
to Philips I
2
S. In all modes, the interface provides up to
18 significant bits of output data per channel. During
standby mode (STDB = LOW), all interface pins are in
their high impedance state. On recovery from standby, the
serial data output SDO is held LOW until valid data is
available from the decimation filter. This time depends on
whether the high-pass filter is selected:
HPEN = 0; T = 1024/f
s
, T = 21.3 ms when f
s
= 48 kHz
HPEN = 1; T = 12288/f
s
, T = 256.0 ms when
f
s
= 48 kHz
Overload detection
The OVLD output is used to indicate when the output data,
in either the left or right channel, is greater than
−
1 dB
(actual figure
−
1.023 dB) of the maximum possible digital
swing. When this condition is detected, the OVLD output is
forced HIGH for at least 512f
s
cycles (10.6 ms at
f
s
= 48 kHz). This time-out is reset for each infringement.
ITEM
CONDITION
VALUE (dB)
Pass band ripple
0 to 0.45f
s
±
0.1
0.45 to 0.47f
s
−
0.5
Stop band
>0.55f
s
−
60
Dynamic range
0 to 0.42f
s
110
Gain
DC
3.52
ITEM
CONDITION
VALUE
(dB)
Pass band ripple
none
Pass band gain
0
Droop
at 0.00042f
s
0.146
Attenuation at DC
at 0.00000036f
s
>40
Dynamic range
0 to 0.45f
s
>110
Standby mode
The STDB pin activates a power saving mode when the
device function is not required. This pin can also be used
as a chip enable.
On a HIGH-to-LOW transition of the STDB pin, the internal
control circuitry starts a timed power-down sequence. This
takes approximately 32 system clock cycles to complete.
Transitions on STDB that are shorter than 32 clock cycles
may have an indeterminate effect. However, the device
will always recover correctly.
During standby, the following occurs:
•
The internal logic clock is disabled
•
The serial interface pins are forced to high impedance
•
The OVLD output is forced LOW
•
The analog circuitry is disabled
•
The nominal external analog node voltages are
maintained by a low-power circuit. This feature ensures
a fast recovery from standby mode.
Note: since the serial interface pins are high impedance
during standby, these pins could be wire-ORed with other
serial interface ICs.
On a LOW-to-HIGH transition, the device reverts back to
normal operation. This process takes approximately
256 system clock cycles. Before SDO is enabled, the
output data is forced LOW. SDO remains LOW until good
data is available from the decimation filter
(see Section “Serial interface”).
The STDB pin has a Schmitt-trigger input. A simple
power-on-reset function can be effected using an external
capacitor to V
SS
and resistor to V
DD
.
TEST1
This pin is used to select the serial interface format in slave
mode.
1996 Jun 17
8
Philips Semiconductors
Objective specification
Bitstream conversion ADC for
digital audio systems
SAA7367
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. V
SSD
and V
SSA
must be connected to a common potential.
QUALITY SPECIFICATION
In accordance with
“SNW-FQ-611-E”. The number of the quality specification can be found in the “Quality Reference
Handbook”. The handbook can be ordered using the code 9397 750 00192.
CHARACTERISTICS
V
DDD
= 4.5 to 5.5 V; V
DDA
= 4.5 to 5.5 V; f
s
= 18 to 50 kHz; T
amb
=
−
40 to +85
°
C; unless otherwise specified.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
V
DDA
analog supply voltage (note 1)
−
0.5
+6.5
V
V
I
DC input voltage
−
0.5
+6.5
V
I
IK
DC input clamp diode current
−
±
20
mA
V
O
DC output voltage
−
0.5
V
DD
+ 0.5
V
I
O
DC output source or sink current
−
±
20
mA
I
DD(tot)
total DC supply current
−
±
0.5
A
I
SStot
total DC supply current
−
±
0.5
A
T
amb
operating ambient temperature
−
40
+85
°
C
T
stg
storage temperature
−
65
+150
°
C
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
DDD
digital supply voltage
4.5
5
5.5
V
I
DDD
digital supply current
f
s
= 48 kHz
−
17
−
mA
V
DDA
analog supply voltage
4.5
5
5.5
V
I
DDA
analog supply current
−
13
−
mA
P
tot
total power dissipation
f
s
= 48 kHz
−
150
−
mW
I
stb
standby supply current
−
160
−
µ
A
P
stb
standby power consumption
−
800
−
µ
W
Digital part: inputs
SFOR, SLAVE
AND
HPEN
V
IL
LOW level input voltage
−
0.5
−
+0.8
V
V
IH
HIGH level input voltage
2.0
−
V
DD
+ 0.5
V
I
LI
input leakage current
−
10
−
+10
µ
A
C
i
input capacitance
−
−
10
pF
1996 Jun 17
9
Philips Semiconductors
Objective specification
Bitstream conversion ADC for
digital audio systems
SAA7367
CKIN
V
IL
LOW level input voltage
−
0.5
−
0.3V
DD
V
V
IH
HIGH level input voltage
0.7V
DD
−
V
DD
+ 0.5
V
I
LI
input leakage current
−
10
−
+10
µ
A
C
i
input capacitance
−
−
10
pF
TEST1
V
IL
LOW level input voltage
−
0.5
−
+0.8
V
V
IH
HIGH level input voltage
2.0
−
V
DD
+ 0.5
V
R
i
internal resistance to V
SS
−
50
−
k
Ω
C
i
input capacitance
−
−
10
pF
TESTB
V
IH
HIGH level input voltage
0.7V
DD
−
V
DD
+ 0.5
V
R
i
internal resistance to V
DD
−
50
−
k
Ω
STDB (S
CHMITT TRIGGER
)
V
IL
LOW level input voltage
−
0.5
−
0.4V
DD
V
V
IH
HIGH level input voltage
0.6V
DD
−
V
DD
+ 0.5
V
V
hys
hysteresis voltage
200
−
−
mV
I
LI
input leakage current
−
10
−
+10
µ
A
C
i
input capacitance
−
−
10
pF
Digital part: inputs/outputs
SWS
AND
SCK
V
IL
LOW level input voltage
−
0.5
−
+0.8
V
V
IH
HIGH level input voltage
2.0
V
DD
+ 0.5
V
I
Ll
3-state leakage current
−
10
−
+10
µ
A
C
i
input capacitance
−
−
10
pF
V
OL
LOW level output voltage
I
O
=
−
400