Low power dual-band GSM transceiver with an image rejecting front-end

2000 Aug 15

Philips Semiconductors

Preliminary speciﬁcation

Low power dual-band GSM transceiver

with an image rejecting front-end

UAA3522HL

FEATURES

•

Dual-band application for Global System for Mobile

communication (GSM) and Digital Cellular

communication Systems (DCS)

•

Low noise and wide dynamic range single Intermediate

Frequency (IF) transceiver

•

More than 30 dB on-chip image rejection in the receiver

•

More than 60 dB gain control range

•

I/Q demodulator with high performance integrated

baseband channel filter

•

High precision I/Q modulator

•

Transmit modulation loop architecture including offset

mixer and phase detector

•

Dual Phase-Locked Loop (PLL) with on-chip IF Voltage

Controlled Oscillator (VCO)

•

Fully differential design minimizing cross-talk and spurii

•

3-wire serial bus interface

•

Functional down to 2.7 V and up to 3.3 V

•

LQFP48 package.

APPLICATIONS

•

GSM 900 MHz hand-held transceiver

•

GSM/DCS dual-band solution with the UAA2077CM

(down to 3.2 V) or UAA2077TS/D (down to 2.7 V).

GENERAL DESCRIPTION

The UAA3522HL integrates the receiver and most of the

transmitter section of a GSM hand-held transceiver. It also

integrates the receiver IF and the transmitter section of a

DCS transceiver.

The receiver comprises an RF and an IF section. The RF

(GSM) front-end amplifies the aerial signal, converts the

chosen channel frequency to an IF of 200 MHz, and also

provides more than 30 dB of image suppression. Some

selectivity is provided at this stage by an off-chip bandpass

pre-filter. The IF section further amplifies the chosen

channel, maintains the gain at the required level,

demodulates the signal into I and Q components, and

provides channel selectivity at a baseband stage using

a high performance integrated low-pass filter. The IF gain

can be varied over a range of more than 60 dB. The offset

at the I and Q outputs can be cancelled out by software

using the 3-wire serial programming bus.

The input Low Noise Amplifier (LNA) can be switched off

via the bus to allow accurate calibration in the offset

cancellation mode.

The transmitter comprises a high precision I/Q modulator

and modulation loop architecture. The I/Q modulator

converts the baseband modulation frequency to the

transmit IF. The modulation loop architecture, which

includes an on-chip offset mixer and phase detector,

controls an external transmit RF VCO which converts the

transmit modulated IF signal to RF.

A receive RF VCO provides the Local Oscillator (LO)

signal to the image rejection mixers in the RF receiver.

An IF VCO provides the LO signal to the I/Q demodulator

and I/Q modulator in the receiver and transmitter sections

respectively.

The frequencies of the RF VCO and the IF VCO are set by

internal PLL circuits, which are programmable via the

3-wire serial bus. The RF and IF PLL comparison

frequencies are 200 kHz and 1 MHz respectively, derived

from a 13 MHz reference signal which has to be supplied

externally. The quadrature RF LO signals required by the

image rejection mixers are obtained using on-chip

Resistor Capacitor (RC) networks. The quadrature IF LO

signals required by the I/Q modulator and I/Q demodulator

are obtained by dividing the frequency of the IF VCO

signal.

The IC can be powered on in either receiver (RX),

transmitter (TX) or synthesizer (SYN) operating mode

depending on the logic level at pins RXON, TXON and

SYNON, respectively. Alternatively, an operating mode

can be selected by software using the 3-wire serial

programming bus. In RX or TX mode, only those sections

of the IC which are required are switched on.

The GSM or DCS band is selected by the 3-wire serial

programming bus. When activating RX mode for DCS

applications, the receiver RF section can be disabled by

software so that only the receiver IF section is

powered-on.

The SYN mode is used to power-on the synthesizer prior

to activating the RX or TX mode. In SYN mode, some

internal LO buffers are also powered-on to minimize the

‘pulling’ effect of the VCO when either the receiver or the

transmitter are switched on.

2000

Aug

Philips Semiconductors

Preliminar

y speciﬁcation

w po

er dual-band GSM tr

ansceiv

with an image rejecting front-end

AA3522HL

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BLOCK DIA

GRAM

andbook, full pagewidth

FCA004

UAA3522HL

UAA2077XM

DIVIDER &

PHASE

SHIFTER

IF VCO

XTAL

PROGRAMMABLE

DIVIDER

PROGRAMMABLE

DIVIDER

BALUN

DIVIDER

4, 5

2, 3

4, 5

2, 3

38, 39

44, 45

30, 31

8, 9

46, 47

IF PHASE/

FREQUENCY

DETECTOR

RF PHASE/

FREQUENCY

DETECTOR

CHARGE

PUMP

IF VCO

400 MHz

REF OSC.

13 MHz

13,

RX/TX

SWITCH

POWER

AMPLIFIER

GSM RF

RX VCO

1080 to 1160

MHz

GSM TX RF VCO

880 to 915 MHz

GSM BAND

925 to 960 MHz

DCS TX RF VCO

1710 to 1785 MHz

DCS RF

RX VCO

1510 to 1680

MHz

1710 to 1785 MHz

DCS BAND

1805 to1880 MHz

CHARGE

PUMP

41,

CHARGE

PUMP

PHASE

DETECTOR

PHASE

SHIFTER

PHASE

SHIFTER

ADDER

BALUN

PHASE

SHIFTER

PHASE

SHIFTER

ADDER

SAW

Fig.1 Block diagram.

2000 Aug 15

Philips Semiconductors

Preliminary speciﬁcation

Low power dual-band GSM transceiver

with an image rejecting front-end

UAA3522HL

PINNING

SYMBOL

PIN

DESCRIPTION

CCIF1

IF section of RF receiver supply

voltage 1

Q path A baseband input/output

Q path B baseband input/output

I path A baseband input/output

I path B baseband input/output

REFAGC

AGC reference resistor

GNDIF2

I/Q modulator and I/Q demodulator

ground 2

RXIIFA

RX IF input A to AGC ampliﬁer

RXIIFB

RX IF input B to AGC ampliﬁer

CCIF2

I/Q modulator and I/Q demodulator

supply voltage 2

TXON

TX mode control pin

CCIFLO

IF LO supply voltage

IFLOC

IF LO signal input from

IF VCO resonator

IFLOE

IF LO signal input from

IF VCO resonator

GNDIFLO

IF LO ground

CPOIF

IF charge pump output

GNDCPIF

IF charge pump and phase

detector ground

CCCPIF

IF charge pump and phase

detector supply voltage

serial programming bus enable

control pin

DATA

serial programming bus data input

CLK

serial programming bus clock input

GNDSYN

synthesizer ground

REFIN

13 MHz reference input

CCSYN

synthesizer supply voltage

CCCPRF

RF charge pump and phase

detector supply voltage

CPORF

RF charge pump output

GNDCP

RF charge pump ground

SYNON

SYN mode control pin

CCRFLO

RF LO section supply voltage

RFLOC

LO signal input from RF VCO

RFLOE

LO signal input from RF VCO

GNDRFLO

RF LO section ground

RXON

RX mode control pin

GNDPHD

transmit modulation loop charge

pump ground

PHDOUT

charge pump output

CCPHD

transmit modulation loop charge

pump supply voltage

RESEXT

reference resistor for transmit

modulation loop

TXIRFA

TX RF VCO signal input

TXIRFB

TX RF VCO signal input

CCRF

RF receiver and transmit

modulation loop supply voltage

RXIRFA

RF receiver input A

RXIRFB

RF receiver input B

GNDRF

RF receiver and transmit

modulation loop ground

TXIFA

transmit IF external ﬁlter A

TXIFB

transmit IF external ﬁlter B

RXOIFA

receiver IF output A

RXOIFB

receiver IF output B

GNDIF1

IF section of RF receiver ground 1

SYMBOL

PIN

DESCRIPTION

2000 Aug 15

Philips Semiconductors

Preliminary speciﬁcation

Low power dual-band GSM transceiver

with an image rejecting front-end

UAA3522HL

FUNCTIONAL DESCRIPTION

RF receiver

The receiver front-end converts the aerial RF signal, in the

GSM band (925 to 960 MHz), to an IF signal of

approximately 200 MHz. The first stage of the receiver is

a symmetrical LNA that is matched to 50

Ω

by an external

balun. The LNA is followed by an image rejection mixer

which suppresses the image by more than 30 dB.

It comprises two mixers in parallel driven by 0

and 90

quadrature LO signals respectively. The IF signal from

one mixer is shifted by 90

with respect to the IF signal

from the other mixer, then both signals are added together

to cancel out the image signal. The resultant IF signal is

fed to the output via a high output impedance

open-collector stage which drives an external Surface

Acoustical Wave (SAW) filter which selects the required

channel.

I/Q demodulator

The signal from the SAW filter enters the I/Q demodulator

section. In addition to I/Q demodulation, this section

performs Automatic Gain Control (AGC) over a range of

60 dB to maintain a constant output level irrespective of

the antenna input level, and also applies additional

channel selectivity at the baseband stage using an

integrated high-order low-pass filter.

The AGC amplifier output can be adjusted for a static

offset of less than 50 mV. Its design prevents the offset

from varying by more than

5 mV. To allow a more

accurate offset calibration, the RF LNA can be switched off

to ensure that no IF signal is present at the AGC amplifier

input during the offset measurement.

I/Q modulator

Baseband I and Q signals are applied to the I/Q modulator

which shifts the modulation spectrum up to the transmit IF.

The I/Q modulator is designed for low harmonic distortion,

low carrier leakage and high image rejection to keep the

phase error as small as possible. Its IF output is loaded by

an integrated low-pass filter and by an external

LC tuned-circuit to prevent unwanted spurii from entering

the phase detector in the transmit modulation loop.

Transmit modulation loop

The analog transmit modulation loop comprises an on-chip

offset mixer and simple phase detector in switching mode

(triangular transfer function) forming an analog PLL with

an off-chip loop filter and transmit RF VCO.

The phase detector output transfers the modulation of the

I/Q IF signal to the off-chip transmit RF VCO making the

analog PLL act as a tracking filter. A PLL of at least

third-order is needed to meet noise requirements at

20 MHz offset from the carrier.

RF and IF LO sections

The active components required for the design of a low

noise IF VCO are provided on-chip. Pins IFLOC and

IFLOE connect the on-chip IF VCO components to an

external resonator and feedback circuit.

A divider and phase shifter divides the frequency of the

IF VCO signal by 2 and splits it into two signals having

phases of respectively 0

and 90

which are both fed to the

I/Q modulator and to the I/Q demodulator. The IF VCO

frequency is twice the IF to suppress the effects of

self-mixing and parasitic VCO modulation.

Pins TXIRFA and TXIRFAB connect an external receive

RF VCO module to the on-chip RF LO section. This

section includes a RC phase shifter which splits the

RF VCO signal into two signals having phases of

respectively 0

and 90

which are both fed to the

RX image rejection mixer.

Dual PLL

An on-chip high performance dual PLL synthesizes the

frequencies of the receive RF VCO and IF VCO signals.

Very low close-in phase noise is achieved which provides

a wide PLL bandwidth with a short settling time.

A dual programmable divider chain reduces the frequency

of the receive RF and IF LO signals to 200 kHz and 1 MHz

respectively. A digital phase/frequency detector compares

their phases to a reference signal derived from an external

13 MHz clock signal. Phase error information is fed back

to both VCOs via the dual charge pump circuit which

adjusts the phase of each VCO signal by either ‘sinking’

current into, or ‘sourcing’ current from, its loop filter

capacitor, phase locking both RF and IF loops. The very

low leakage current of the dual charge pump circuit

ensures that any spurii are negligible.

Operating modes

ASIC OPERATING MODES

The circuit can be powered on in one of four operating

modes in which different parts of the device are enabled or

disabled. The four operating modes are called Idle, RX,

TX and SYN, and are selected by the hardware control

voltage level applied to pins RXON, TXON and SYNON.

2000 Aug 15

Philips Semiconductors

Preliminary speciﬁcation

Low power dual-band GSM transceiver

with an image rejecting front-end

UAA3522HL

The synthesizer, receiver and transmitter cannot all be on

at the same time. Table 1 shows which parts of the device

are enabled (on) or disabled (off) in each mode.

Table 1

Operating modes

The synthesizer includes the oscillators and LO buffers

common to the receive and transmit sections. The receiver

includes the RF section and the I/Q demodulator. When

the receiver is on, the LNA can be switched off to allow

DC offset compensation to be performed. The RF section

can also be switched off for DCS applications. See Section

“Receiver power status control”.

ECEIVER POWER STATUS CONTROL

•

DC offset compensation: This feature allows the

DC offset of the receiver output to be set accurately.

When the receiver is on, the LNA can be switched off to

isolate the antenna input from the I/Q demodulator

input. The offset at the I and Q outputs can be

independently reduced to less than 50 mV by

adequately programming two 5-bit data registers,

see Table 4 “Register bit allocation”. The LNA is

switched on or off by the status of bit LNA (see Table 2).

•

Disabling RF section: For DCS applications, the RF

section can be disabled in RX mode. The same

IF circuits are used for both GSM and DCS applications

to avoid duplication. For DCS applications using the

UAA2077XM, for example, the RF section of the

UAA3522HL does not have to be powered on.

The RF section is enabled or disabled by the status of

bit RF when the RX mode is activated (see Table 3).

Table 2

Bit LNA status

Table 3

Bit RF status

Programming

ERIAL PROGRAMMING BUS

A simple 3-wire unidirectional serial bus is used for

programming the IC. The lines are called DATA, CLK

and EN (enable). Programming data is sent to the IC in

bursts which are separated from each other by EN.

Programming clock edges are ignored until EN goes

active LOW. The data is loaded into the addressed register

when EN returns inactive HIGH, and when the CLK is in

either state, without affecting the data in the register.

The register only holds the last 18 bits that are serially

clocked into the IC.

Additional leading bits are ignored, and no check is made

on the number of clock pulses received. The fully static

CMOS design uses virtually no current when the bus is

inactive. It can always accept new programming data even

when both synthesizers are powered-off.

ATA FORMAT

Data is loaded into the register with the most significant bit

(MSB) first. The first 14 bits are data, while the last 4 bits

are the register address. The address bits are decoded on

the rising edge of EN. This internally generates a load

pulse to store the data in the addressed register.

To ensure that data loads correctly after the device has

powered-up, EN should be held LOW and only taken HIGH

after the appropriate register has been loaded.

The EN pulse is inhibited during the period when data is

read by the frequency dividers to prevent divider ratio data

from being read incorrectly. This state is guaranteed by

always allowing for a minimum EN pulse width after data

transfer.

MODE

POWER STATUS

SYNTHESIZER RECEIVER TRANSMITTER

Idle

off

SYN

off

BIT LNA STATUS

POWER STATUS OF BIT LNA

off

BIT RF STATUS

POWER STATUS OF

RECEIVER RF SECTION

IN RX MODE

on (GSM)

off (DCS)

2000

Aug

Philips Semiconductors

Preliminar

y speciﬁcation

w po

er dual-band GSM tr

ansceiv

with an image rejecting front-end

AA3522HL

Table 4

X = don’t care; MSB = Most Signiﬁcant Bit; LSB = Least Signiﬁcant Bit.

Notes

1. Bit LNA: 1 = LNA ON in RX mode; 0 = LNA OFF in RX mode.

2. Bits Q sign and I sign = polarity of offset at Q/I channel outputs: 0 = negative offset step (output A with respect to output B); 1 = positive offset step

(output A with respect to output B).

3. Bit IF RD: 0 = frequency dividers programmed for GSM applications; 1 = frequency dividers programmed for DCS applications.

4. Bit IF VCO: 0 = IF LO buffer ON (external IF LO source connected); 1 = IF VCO ON (external IF LO source not connected).

5. Bit RF: 1 = RF section ON when RX mode is activated; 0 = RF section OFF when RX mode is activated.

6. This address must not be used. Data bits to be defined.

DATA BITS

ADDRESS BITS

FIRST

BIT

LAST

BIT

MSB

IF LO frequency divider ratio

LSB

MSB

RF LO frequency divider ratio

LSB

LNA

(1)

MSB

AGC ampliﬁer gain (RX mode)

see Table 5

LSB

MSB

Q output offset adjust

LSB

Q sign

(2)

MSB

I output offset adjust

LSB

I sign

(2)

IF RD

(3)

IF VCO

(4)

(5)

SYN ON

RX ON

TX ON

For test purposes only

(6)

2000 Aug 15

Philips Semiconductors

Preliminary speciﬁcation

Low power dual-band GSM transceiver

with an image rejecting front-end

UAA3522HL

Table 5

AGC ampliﬁer gain register look-up table

All codes not included in the table are forbidden.

Note

1. Voltage gain is defined as the differential baseband output voltage (either at pins IA/IB or pins QA/QB) divided by the

differential input voltage at pins RXIIFA and RXIIFB.

BIT 5 (MSB)

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0 (LSB)

AGC AMPLIFIER

GAIN (dB)

(1)

−

+11

+13

+15

+17

+19

+21

+23

+25

+27

+29

+31

+33

+35