Image rejecting front-end for DECT applications

1996 Jul 04

Philips Semiconductors

Product speciﬁcation

Image rejecting front-end

for DECT applications

UAA2077AM

FEATURES

•

Low-noise, wide dynamic range amplifier

•

Very low noise figure

•

Dual balanced mixer for over 25 dB on-chip image

rejection

•

IF I/Q combiner at 110 MHz

•

On-chip quadrature network

•

RX fast on/off power-down mode

•

Shrink small outline packaging

•

Very small application (no image filter).

APPLICATIONS

•

1800 MHz front-end for DECT hand-portable

equipment

•

Compact digital mobile communication equipment

•

TDMA receivers.

GENERAL DESCRIPTION

UAA2077AM contains a high frequency low noise receiver

front-end intended to be used in DECT mobile telephones.

Designed in an advanced BiCMOS process it combines

high performance with low power consumption and a high

degree of integration, thus reducing external component

costs and total front-end size.

The main advantage of the UAA2077AM is its ability to

provide over 25 dB of image rejection. Consequently, the

image filter between the LNA and the mixer is suppressed.

Image rejection is achieved in the internal architecture by

two RF mixers in quadrature and two all-pass filters in I

and Q IF channels that phase shift the IF by 45

and 135

respectively. The two phase shifted IFs are recombined

and buffered to furnish the IF output signal.

For instance, signals presented at the RF input at LO + IF

frequency are rejected through this signal processing

while signals at LO

−

IF frequency can form the IF signal.

An internal switch enables the upper or lower image

frequency to be rejected.

The receiver section consists of a low-noise amplifier that

drives a quadrature mixer pair. The IF amplifier has

on-chip 45

and 135

phase shifting and a combining

network for image rejection. The IF driver has differential

open-collector type outputs.

The LO part consists of an internal all-pass type phase

shifter to provide quadrature LO signals to the receive

mixers.The centre frequency of the phase shifter is

adjustable for maximum image rejection in a given band.

The all-pass filters outputs are buffered before being fed to

the receive mixers. All RF and IF inputs or outputs are

balanced.

Two pins RXON and SXON are used to control the

different power-down modes. A special mode of operation

called synthesizer-on mode (SX mode), controlled by pin

SXON can be used to minimize the LO pulling when the

receiver is turned on. When SXON is HIGH, all internal

buffers on the LO path are turned on. Pin SBS allows a

selection of whether to reject the upper or lower image

frequency. Special care has been taken for fast power-up

switching.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

supply voltage

amb

= 0 to +70

3.15

4.0

5.3

over full temperature range

3.6

4.0

5.3

CC(RX)

receive supply current

21.5

26.5

33.5

CC(PD)

supply current in power-down

−

0.2

amb

operating ambient temperature

−

+25

+85

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

UAA2077AM

SSOP20

plastic shrink small outline package; 20 leads; body width 4.4 mm

SOT266-1

1996 Jul 04

Philips Semiconductors

Product speciﬁcation

Image rejecting front-end

for DECT applications

UAA2077AM

PINNING

SYMBOL

PIN

DESCRIPTION

n.c.

not connected

n.c.

not connected

CCLNA

supply voltage for LNA and IF parts

n.c.

not connected

RFINA

RF input A (balanced)

RFINB

RF input B (balanced)

n.c.

not connected

LNAGND

ground for LNA and IF parts

SXON

SX mode enable (see Table 1)

QUADLO

input voltage for LO quadrature

trimming

SBS

sideband selection

RXON

RX mode enable (see Table 1)

LOINB

LO input B (balanced)

LOINA

LO input A (balanced)

CCLO

supply voltage for LO parts

LOGND

ground for LO parts

IFA

IF output A (balanced)

IFB

IF output B (balanced)

n.c.

not connected

n.c.

not connected

Fig.2 Pin configuration.

handbook, halfpage

UAA2077AM

MBH151

n.c.

RFINA

RFINB

LNAGND

SXON

VQUADLO

SBS

RXON

LOINB

LOINA

LOGND

IFA

IFB

n.c.

VCCLNA

VCCLO

FUNCTIONAL DESCRIPTION

Receive section

The circuit contains a low-noise amplifier followed by two

high dynamic range mixers. These mixers are of the

Gilbert-cell type, the whole internal architecture is fully

differential.

The local oscillator, shifted in phase to 45

and 135

mixes the amplified RF to create I and Q channels.

The two I and Q channels are buffered, phase shifted by

and 135

respectively, amplified and recombined

internally to realize the image rejection.

Pin SBS allows sideband selection:

•

> f

(SBS = 1)

•

< f

(SBS = 0).

where f

is the frequency of the wanted signal.

Balanced signal interfaces are used for minimizing

crosstalk due to package parasitics.

The IF output is differential and of the open-collector type.

Typical application will load the output with a differential

1 k

Ω

load; for example, a 1 k

Ω

resistor load at each IF

output, plus a differential 2 k

Ω

load consisting of the input

impedance of the IF filter or the input impedance of the

matching network for the IF filter. The power gain refers to

the available power on this 2 k

Ω

load. The path to V

for

the DC current should be achieved via tuning inductors.

The output voltage is limited to V

+ 3V

or 3 diode

forward voltage drops.

Fast switching, on/off, of the receive section is controlled

by the hardware input RXON.

1996 Jul 04

Philips Semiconductors

Product speciﬁcation

Image rejecting front-end

for DECT applications

UAA2077AM

Fig.3 Block diagram, receive section.

handbook, full pagewidth

MBH152

LNA

COMBINER

amplifier

MIXER

RXON

LOIN

IFA

IFB

SBS

RFINA

RFINB

LNAGND

VCCLNA

135

Local oscillator section

The local oscillator (LO) input directly drives the two

internal all-pass networks to provide quadrature LO to the

receive mixers.

The centre frequency of the receive band is adjustable by

the voltage on pin V

QUADLO

. This should be achieved by

connecting a resistor between V

QUADLO

and V

. Over

25 dB of image rejection can be obtained by an optimum

resistor value.

A synthesizer-on (SX) mode is used to power-up the LO

input buffers, thus minimizing the pulling effect on the

external VCO when entering receive mode. This mode is

active when SXON = 1.

There are no internal biassing components attached to the

pins LOINA and LOINB. These pins are connected by

capacitors to the internal phase shifting network.

Fig.4 Block diagram, LO section.

handbook, halfpage

MBH153

LOINB

to RX

LOINA

QUAD

LOGND

VCCLO

VQUADLO

1996 Jul 04

Philips Semiconductors

Product speciﬁcation

Image rejecting front-end

for DECT applications

UAA2077AM

Table 1 Control of power status

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

THERMAL CHARACTERISTICS

HANDLING

Every pin withstands the ESD test in accordance with

“MIL-STD-883C Class 2 (method 3015.5)”.

DC CHARACTERISTICS

= 4.0 V; T

amb

= 25

C; unless otherwise speciﬁed.

EXTERNAL PIN LEVEL

CIRCUIT MODE OF OPERATION

RXON

SXON

LOW

power-down mode

HIGH

RX mode (receive and LO sections on)

LOW

HIGH

SX mode (only LO section on)

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

supply voltage

−

∆

GND

difference in ground supply voltage applied between LOGND and LNAGND

−

0.6

l(max)

maximum power input

−

dBm

j(max)

maximum operating junction temperature

−

150

max

maximum power dissipation

−

250

stg

IC storage temperature

−

+150

SYMBOL

PARAMETER

VALUE

UNIT

th j-a

thermal resistance from junction to ambient in free air

120

K/W

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Pins V

CCLNA

and V

CCLO

supply voltage

amb

= 0 to +70

3.15

4.0

5.3

over full temperature range 3.6

4.0

5.3

CC(RX)

supply current in RX mode

21.5

26.5

33.5

CC(PD)

supply current in power-down mode

−

0.2

CC(SX)

supply current in SX mode

Pins RXON, SXON and SBS

CMOS threshold voltage

note 1

−

1.25

−

HIGH level input voltage

0.7V

−

LOW level input voltage

−

0.3

−

+0.8

HIGH level static input current

pin at V

−

0.4 V

−

LOW level static input current

pin at 0.4 V

−

1996 Jul 04

Philips Semiconductors

Product speciﬁcation

Image rejecting front-end

for DECT applications

UAA2077AM

Note

1. The referenced inputs should be connected to a valid CMOS input level.

AC CHARACTERISTICS

= 4.0 V; T

amb

−

30 to +85

C; unless otherwise speciﬁed.

Pins RFINA and RFINB

DC input voltage level

receive section on

−

2.0

−

Pins IFA and IFB

DC output current

receive section on

−

2.5

−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Receive section (receive section enabled)

iRX

RF input resistance

(real part of the parallel input

impedance)

balanced; at 1890 MHz

−

Ω

iRX

RF input capacitance

(imaginary part of the parallel

input impedance)

balanced; at 1890 MHz

−

iRX

RF input frequency

1880

−

1900

MHz

iRX

return loss on matched RF

input

balanced; note 1

−

conversion power gain

differential RF inputs to

differential IF outputs loaded to

1 k

Ω

differential

rip

gain ripple as a function of RF

frequency

note 2

−

0.2

−

∆

G/T

gain variation with temperature T

amb

−

30 to +25

C; note 2

−

+10

mdB

/°

amb

= +25 to +85

C; note 2

−

mdB

/°

CP1

1 dB compression point

differential RF inputs to

differential IF outputs; note 1

−

dBm

DES3

3 dB desensitisation point

interferer frequency offset:

3 MHz; differential RF inputs to

differential IF outputs; note 1

−

dBm

interferer frequency offset:

20 MHz; differential RF inputs to

differential IF outputs; note 1

−

dBm

IP2D

order intercept point

differential RF inputs to

differential IF outputs; note 2

−

dBm

IP3

order intercept point

differential RF inputs to

differential IF outputs; note 2

−

dBm

overall noise ﬁgure

differential RF inputs to

differential IF outputs;

notes 2 and 3

−

4.3

5.0

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Jul 04

Philips Semiconductors

Product speciﬁcation

Image rejecting front-end

for DECT applications

UAA2077AM

Notes

1. Measured and guaranteed only on UAA2077AM demonstration board at T

amb

= 25

2. Measured and guaranteed only on UAA2077AM demonstration board.

3. This value includes printed-circuit board and balun losses.

4. Measured and guaranteed only on UAA2077AM demonstration board at T

amb

= 25

C. V

QUADLO

open-circuit.

LRX

typical application IF output

load impedance

balanced

−

Ω

oRX

return loss on matched IF

output

balanced; note 1

−

oRX

IF frequency

−

110

−

MHz

rejection of image frequency

< f

; f

= 110 MHz; note 4

−

Local oscillator section (receive section enabled)

iLO

LO input frequency

1770

−

2010

MHz

iLO

LO input resistance

(real part of the parallel input

impedance)

balanced; at 1780 MHz

−

Ω

iLO

LO input capacitance

(imaginary part of the parallel

input impedance)

balanced; at 1780 MHz

−

iLO

return loss on matched LO

input (including power-down

mode)

note 1

−

∆

iLO

return loss variation ratio

between SX and RX modes

linear S

variation; note 1

−

iLO

LO input power level

−

dBm

reverse isolation

LOIN to RFIN at LO frequency;

note 2

−

Timing

start

start-up time of each block

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996

Jul

Philips Semiconductors

Product speciﬁcation

Image rejecting front-end

for DECT applications

UAA2077AM

APPLICA

TION INFORMA

TION

handbook, full pagewidth

MGC631 - 1

1200

Ω

220

L11

220

L12

4 V

1200

Ω

6.8 pF

C22

120 pF

C23

6.8 pF

C24

IFA

IFB

120 nH

L13

120 nH

L14

C25

22 pF

C26

22 pF

110 MHz

UAA2077AM

C27

8.2 pF

C28

1 nF

4 V

C19

8.2 pF

C29

8.2 pF

C21

1.8 pF

3.3 nH

C20

1.8 pF

LOIN

1770 to 1790

MHz

3.3 nH

L10

8.2

560

Ω

RXON

4 V

8.2

560

Ω

SBS

8.2

560

Ω

SXON

C30

8.2 pF

C31

82 pF

QUADLO

5.6 nH

C14 1.2 pF

1.2 pF

RFIN

1880 to1900

MHz

5.6 nH

8.2 pF