PSD4XX/ZPSD4XX FAMILY FIELD-PROGRAMMABLE MICROCONTROLLER PERIPHERALS

PSD4XX Family

PSD4XX/ZPSD4XX

Field-Programmable Microcontroller Peripherals

Table of Contents

Introduction ...........................................................................................................................................................1

Key Features ........................................................................................................................................................2

Notation ................................................................................................................................................................3

Zero-Power Background .......................................................................................................................................3

Integrated Power Management

Operation ........................................................................................................5

Design Flow ..........................................................................................................................................................6

PSD4XX Family ....................................................................................................................................................7

Table 2. PSD4XX Pin Descriptions......................................................................................................................8

The PSD4XX Architecture ..................................................................................................................................10

9.1 The ZPLD Block..........................................................................................................................................10

9.1.1 The PSD4XXA1 ZPLD Block............................................................................................................10

9.1.1.1

The DPLD ..........................................................................................................................12

9.1.1.2

The GPLD ..........................................................................................................................13

9.1.1.3

TPA Macrocell Structure ...................................................................................................13

9.1.1.4

Port B Macrocell Structure .................................................................................................17

9.1.1.5

The ZPLD Power Management..........................................................................................18

9.1.2 The PSD4XXA2 ZPLD Block............................................................................................................22

9.1.2.1

The DPLD ..........................................................................................................................24

9.1.2.2

The GPLD ..........................................................................................................................26

9.1.2.3

Port A Macrocell Structure .................................................................................................26

9.1.2.4

Port B Macrocell Structure .................................................................................................30

9.1.2.5

Port E Macrocell Structure .................................................................................................33

9.1.2.6

The ZPLD Power Management..........................................................................................34

9.2 Bus Interface...............................................................................................................................................37

9.2.1 Bus Interface Configuration ..............................................................................................................37

9.2.2 PSD4XX Interface to a Multiplexed Bus ...........................................................................................38

9.2.3 PSD4XX Interface to Non-Multiplexed Bus ......................................................................................38

9.2.4 Data Byte Enable..............................................................................................................................42

9.2.5 Optional Features .............................................................................................................................43

9.2.6 Bus Interface Examples....................................................................................................................43

9.3 I/O Ports......................................................................................................................................................48

9.3.1 Standard MCU I/O ............................................................................................................................48

9.3.2 PLD I/O ...........................................................................................................................................48

9.3.3 Address Out......................................................................................................................................49

9.3.4 Address In ........................................................................................................................................49

9.3.5 Data Port ..........................................................................................................................................49

9.3.6 Alternate Function In ........................................................................................................................49

9.3.7 Peripheral I/O ...................................................................................................................................50

9.3.8 Open Drain Outputs..........................................................................................................................50

9.3.9 Port Registers...................................................................................................................................51

9.3.10 Port A – Functionality and Structure.................................................................................................54

9.3.11 Port B – Functionality and Structure.................................................................................................54

9.3.12 Port C and Port D – Functionality and Structure ..............................................................................57

9.3.13 Port E – Functionality and Structure.................................................................................................57

9.4 Memory Block .............................................................................................................................................61

9.4.1 EPROM ............................................................................................................................................61

9.4.2 SRAM ...............................................................................................................................................61

PSD4XX Family

PSD4XX/ZPSD4XX

Field-Programmable Microcontroller Peripherals

Table of Contents

(cont.)

9.4.3 Memory Select Map..........................................................................................................................61

9.4.4 Memory Select Map for 8031 Application.........................................................................................62

9.4.5 Peripheral I/O ...................................................................................................................................65

9.5 Power Management Unit ............................................................................................................................67

9.5.1 Standby Mode ..................................................................................................................................67

9.5.2 Other Power Saving Options ............................................................................................................70

10.0 Page Register .....................................................................................................................................................72

11.0 Security Protection..............................................................................................................................................72

12.0 System Configuration .........................................................................................................................................73

12.1

Reset Input ..............................................................................................................................................76

12.2

ZPLD and Memory During Reset.............................................................................................................76

12.3

Register Values During and After Reset..................................................................................................76

12.4

ZPLD Macrocell Initialization ...................................................................................................................76

13.0 Specifications......................................................................................................................................................77

13.1

Absolute Maximum Ratings .....................................................................................................................77

13.2

Operating Range .....................................................................................................................................77

13.3

Recommended Operating Conditions......................................................................................................77

13.4

AC/DC Parameters ..................................................................................................................................78

13.5

Example of ZPSD4XX Typical Power Calculation at V

= 5.0 V ...........................................................80

13.6

DC Characteristics (5 V ± 10% versions) ................................................................................................81

13.7

AC/DC Parameters – ZPLD Timing Parameters .....................................................................................82

13.8

Microcontroller Interface – AC/DC Parameters .......................................................................................84

13.9

DC Characteristics (ZPSD4XXV Versions) (3.0 V ± 10% versions) ........................................................88

13.10 AC/DC Parameters – ZPLD Timing Parameters (3.0 V ± 10% versions)................................................89

13.11 Microcontroller Interface – AC/DC Parameters (3.0 V± 10% versions)...................................................91

14.0 Timing Diagrams.................................................................................................................................................95

15.0 Pin Capacitance................................................................................................................................................102

16.0 AC Testing ........................................................................................................................................................102

17.0 Erasure and Programming................................................................................................................................102

18.0 PSD4XX Pin Assignments ................................................................................................................................103

19.0 Package Information .........................................................................................................................................105

20.0 PSD4XX Product Ordering Information ............................................................................................................110

20.1

PSD4XX Family – Selector Guide .........................................................................................................110

20.2

Part Number Construction .....................................................................................................................111

20.3

Ordering Information..............................................................................................................................111

1.0

Introduction

Programmable Peripheral

PSD4XX Family

Field-Programmable Microcontroller Peripherals

The PSD4XX family is a microcontroller peripheral that integrates high-performance and

user-configurable blocks of EPROM, programmable logic, and SRAM into one part.

The PSD4XX products also provide a powerful microcontroller interface that eliminates the

need for external “glue logic”. The no “glue logic” concept provides a user-programmable

interface to a variety of 8- and 16-bit (multiplexed or non-multiplexed) microcontrollers that

is easy to use. The part’s integration, small form factor, low power consumption, and ease

of use make it the ideal part for interfacing to virtually any microcontroller.

The PSD4XX provides two Zero-power PLDs (ZPLD): a Decode PLD (DPLD) and a

General-purpose PLD (GPLD). A configuration bit (Turbo) can be set by the MCU, and will

automatically place the ZPLDs into Standby Mode if no inputs are changing. The ZPLDs are

designed to consume minimum power using Zero-power CMOS technology that uses only

10 µA (typical) standby current. Unused product terms are automatically disabled, also

reducing power, regardless of the Turbo bit setting.

The main function of the DPLD is to perform address decoding for the internal I/O ports,

EPROM, and SRAM. The address decoding can be based on up to 24 bits of address

inputs, control signals (RD, WR, PSEN, etc.), and internal page logic. The DPLD supports

separate program and data spaces (for 8031 compatible MCUs).

The General-purpose PLD (GPLD) can be used to implement various logic functions

defined by the user, such as:

•

State machines

•

Loadable counters and shift registers

•

Inter-processor mailbox

•

External control logic (chip selects, output enables, etc.).

The GPLD has access to up to 59 inputs, 118 product terms, 24 macrocells, and 24 I/O

pins.

PSD4XX Family

1.0

Introduction

(cont.)

The PSD4XX has 40 I/O pins that are divided among 5 ports. Each I/O pin can be

individually configured to provide many functions, including the following:

•

MCU I/O

•

GPLD I/O

•

Latched address output (for MCUs with multiplexed data bus)

•

Data bus (for MCUs with non-multiplexed data bus).

The PSD4XX can easily interface with virtually any 8- or 16-bit microcontroller with a

multiplexed or non-multiplexed bus. All of the MCU control signals are connected to the

ZPLDs, enabling the user to generate signals for external devices.

The PSD4XX provides between 256 Kbits and 1 Mbit of EPROM that is divided in to four

equal-sized blocks. Each block can occupy a different address location, allowing for

versatile address mapping. The access time of the EPROM includes the address latching

and DPLD decoding.

The PSD4XX has an optional 16 Kbit SRAM that can be battery-backed by connecting a

battery to the Vstby pin. The battery will protect the contents of the SRAM in the event of a

power failure. Therefore, you can place data in the SRAM that you want to keep after the

power is switched off. Power switchover to the battery automatically occurs when V

drops

below V

stby

A four-bit Page Register enables easy access to the I/O section, EPROM, and SRAM for

microcontrollers with limited address space. The Page Register outputs are connected to

both ZPLDs and thus can also be used for external paging schemes.

The Power Management Unit (PMU) of the PSD4XX enables the user to control the

power consumption on selected functional blocks, based on system requirements.

For microcontrollers that do not generate a chip select input for the PSD, the Automatic

Power-Down (APD) unit of the PMU can be setup to enable the PSD to enter Power Down

Mode or Sleep Mode, based on the inactivity of ALE (or AS).

Implementing your design has never been easier than with PSDsoft—ST’s software

development suite. Using PSDsoft, you can do the following:

•

Configure your PSD4XX to work with virtually any microcontroller

•

Specify what you want implemented in the programmable logic using a design file

•

Simulate your design

•

Download your design to the part using a programmer.

2.0

Key Features

Single-chip programmable peripheral for microcontroller-based applications

256K to 1 Mbit of UV EPROM with the following features:

•

Configurable as 32, 64, or 128 K x 8; or as 16, 32, or 64 K x 16

•

Divided into four equally-sized mappable blocks for optimized address mapping

•

As fast as 70 ns access time, which includes address decoding

•

Built-in Zero-power technology

16 Kbit SRAM is configurable as 2K x 8 or 1K x 16. The access time can be as

quick as 70 ns, including address decoding. The contents of the SRAM can be

battery-backed by connecting a battery to the Vstby pin. The SRAM also has built-in

Zero-power technology.

40 I/O pins (divided into five 8-bit ports) that can be individually configured for:

•

Standard MCU I/O

•

PLD/macrocell I/O

•

Latched address output

•

High-order address inputs

•

Special function I/O

•

Open-drain output

PSD4XX Family

2.0

Key Features

Two Zero-power Programmable Logic Devices (ZPLDs): the Decode PLD (DPLD) and

the General-purpose PLD (GPLD) can be used for:

•

Up to 59 Input and 126 output product terms

•

24 Macrocells and I/O

•

Decode up to 16 MB of address

•

State machines and state logic

•

Generate external signals (chip selects, bus interface, etc.)

Microcontroller logic that eliminates the need for external “glue logic” has the following

features:

•

Ability to interface to multiplexed and non-multiplexed buses

•

Built-in address latches for multiplexed address/data bus

•

ALE and Reset polarity are programmable

•

Multiple configurations are possible for interface to many different microcontrollers

Page logic is connected to the ZPLDs and expands the MCU address space to up to

16 times

Programmable power management allows:

•

SRAM, EPROM, and ZPLDs to enter standby mode automatically

•

Disabling of the clock input to the ZPLDs

•

ZPLDs to enter a special low power mode (Sleep Mode), based on Turbo bit setting

A security bit prevents reading the PSD4XX configuration and the ZPLD contents.

Setting this bit will prevent the device from being copied on a device programmer.

Built-in security enables the user to block read accesses from a device programmer

Package choices include 68-pin PLCC, 68-pin CLDCC, and 80-pin TQFP

Programmable polarity Reset output (includes hysteresis), based on Reset input

Simple, menu-driven software (PSDsoft) allows configuration and design entry on a PC.

3.0

Notation

Throughout this data sheet, references are made to the PSD4XX. In most cases, these

references also cover the ZPSD4XX and ZPSD4XXV products. Exceptions will be noted.

The main difference between the ZPSD4XX and the PSD4XX is the standby current (Isb).

The ZPSD4XX devices have been rated for a lower standby current. Also, there is no

low-voltage version of the PSD4XX. There is only the low-voltage version of the ZPSD4XX,

which has a V suffix.

Portable and battery powered systems have recently become major embedded control

application segments. As a result, the demand for electronic components having extremely

low power consumption has increased dramatically. Recognizing this need, ST

has developed a new Zero Power technology. PSD4XX products virtually eliminate the DC

component of power consumption reducing it to standby levels. Eliminating the DC

component is the basis for the words “Zero Power”. PSD4XX products also minimize the

AC power component when the chip is changing states. The result is a programmable

microcontroller peripheral family that replaces discrete circuit functions while drawing

minimal current.

4.0

Zero-Power

Background

PSD4XX Family

5.0

Integrated

Power

Management

Operation

Upon each address or logic input change to the ZPSD, the device powers up from low

power standby for a short time. Then the ZPSD consumes only the necessary power to

deliver new logic or memory data to its outputs as a response to the input change. After the

new outputs are stable, the ZPSD latches them and automatically reverts back to standby

mode. The I

current flowing during standby mode and during DC operation is identical

and is only a few microamperes.

The ZPSD automatically reduces its DC current drain to these low levels and does not

require controlling by the CSI (Chip Select Input). Disabling the CSI pin unconditionally

forces the ZPSD to standby mode independent of other input transitions.

The only significant power consumption in the ZPSD occurs during AC operation.

The ZPSD contains the first architecture to apply zero power techniques to memory and

logic blocks.

Figure 2 compares ZPSD Zero-power operation to the operation of a discrete solution.

A standard microcontroller (MCU) bus cycle usually starts with an ALE (or AS) pulse and

the generation of an address. The ZPSD detects the address transition and powers up for a

short time. The ZPSD then latches the outputs of the PAD, EPROM and SRAM to the new

values. After finishing these operations, the ZPSD shuts off its internal power, entering

standby mode. The time taken for the entire cycle is less than the ZPSD’s “access time.”

The ZPSD will stay in standby mode if inputs do not change between bus cycles. In an

alternate system implementation using discrete EPROM, SRAM, and other discrete

components, the system will consume operating power during the entire bus cycle. This is

because the chip select inputs on the memory devices are usually active throughout the

entire cycle. The AC power consumption of the ZPLD may be calculated using the

composite frequency of the MCU address and control signals, as well as any other logic

inputs to the ZPLD.

NOTE: The ZPSD4XX is rated for lower standby current (I

) than the PSD4XX.

ALE

DISCRETE EPROM, SRAM & LOGIC

ADDRESS

EPROM

ACCESS

SRAM

ACCESS

EPROM

ACCESS

ZPSD

TIME

Figure 2. Zero-Power Operation vs. Discrete Implementation

PSD4XX Family

Figure 3. PSDsoft Development Tools

PSDsilos III™

SILOSIII

CHIP SIMULATION

PSD Programmer

PSDpro/MagicPro

CHIP PROGRAMMING

PSD Compiler

(ZPLD FITTING, ADDRESS TRANSLATION)

PSDabel™

ZPLD DESCRIPTION

(STATE MACHINE, DECODING)

PSDsoft

Development Software

PSD Configuration

CHIP CONFIGURATION

THIRD PARTY

PROGRAMMERS

CODE FILE

Shown in Figure 3 (below) is the software design flow for a PSD4XX device.

PSDsoft—ST’s software development suite—is used throughout the design phase. You

start with a design file that is written in PSDabel—a high-level hardware description

language (HDL). Before you compile your design, you must also configure the PSD4XX so

it knows what signals to expect from your microprocessor and what pre-runtime options

should be set (such as the security bit).

Once you have a design file and have configured the device, you are ready to run the Fitter

and Address Translator. The Fitter accepts input from PSDabel and PSD Configuration,

synthesizes this user logic and configuration, and fits the design to the PSD silicon. The

Address Translator process allows the user to map the MCU firmware from a cross-

compiler (in Intel HEX or S-Record format) into the NVM memory blocks within the PSD. As

a result, the MCU firmware is merged with the logic and configuration definition of the PSD.

The output of the Address Translator and the Fitter is the required object file that is used by

a programmer to program the PSD device. The object file includes chip configuration, the

PLD fusemap, and MCU firmware information.

PSDsilosIII is an optional program that provides functional chip-level simulation of the

PSD4XX. PSDsoft automatically creates files for input to the simulator. These files convey

relevant design information to the simulator. As a result, the user only has to create a

stimulus file since all of the signals and node names are taken from the design file.

6.0

Design Flow

PSD4XX Family

Pin Name

Pin Function

Type

Function Descriptions

ADIO0 – ADIO15

Address/data bus

I/O

1. Address/data bus, multiplexed

bus mode

2. Address bus, non-multiplexed

bus mode

Multiple Names

Multiple functions

1. Read

1. Read signal

2. E

2. E signal (Clock)

3. DS

3. Data strobe signal

4. LDS

4. Low byte data strobe

Multiple Names

Multiple functions

1. WR

1. Write signal

2. R/W

2. Read-write signal

3. WRL

3. Low byte write signal

CSI

Chip Select Input

Active low, select PSD4XX

standby mode if high.

RESET

Reset Input

Reset I/O ports, ZPLD/macrocells,

and Configuration Registers.

Active low.

CLKIN

Input clock

Clock input to ZPLD macrocells,

ZPLD Array and APD counter.

Connect to ground if Clock Input

not used.

PA0 – PA7

I/O Port A

I/O

Multiple functions

1. I/O port

2. ZPLD/macrocell I/O port

3. Latched address outputs

(PA0 – PA7)

→

(A0 – A7)

4. High address inputs (A16 – A23)

PB0 – PB7

I/O Port B

I/O

Multiple functions

1. I/O port

2. ZPLD/macrocell I/O port

3. Latched address outputs

(PB0–PB7)

→

(A0–A7) or (A8–A15)

PC0 – PC7

I/O Port C

I/O

Multiple functions

CMOS

1. I/O port

2. ZPLD input port

3. Latched address outputs

(PC0 – PC7)

→

(A0–A7)

4. Data Port (D0 – D7,

non-multiplexed bus)

PD0 – PD7

I/O Port D

I/O

Multiple functions

CMOS

1. I/O port

2. ZPLD input port

3. Latched address outputs

(PD0–PD7)

→

(A0–A7) or (A8–A15)

4. Data Port (D8 –D15,

non-multiplexed bus)

8.0

Table 2.

PSD4XX Pin

Descriptions

The following table describes the pin names and pin functions of the PSD4XX. Pins that

have multiple names and/or functions are defined by user configuration.

Available only in PSD4XXA2 and ZPSD4XXA2 Series.

PSD4XX Family

Pin Name

Pin Function

Type

Function Descriptions

PE0

Port PE, pin 0

I/O

Multiple functions

1. BHE

1. High byte enable, 16 bit data

2. PSEN

2. Read program memory, 8031 signal

3. WRH

3. Write high data byte

4. UDS

4. Upper Data Strobe

5. SIZ0

5. Byte enable, 68300 signal

6. PE0

6. I/O pin

7. PE0

7. ZPLD I/O pin

8. PE0

8. Latched Address Out – A0

PE1

Port PE, pin 1

I/O

Multiple functions

1. ALE

1. Address strobe

2. PE1

2. I/O pin

3. PE1

3. ZPLD I/O pin

4. PE1

4. Latched Address Out – A1

PE2

Port PE, pin 2

Multiple functions

1. PE2

I/O

1. I/O pin

2. PE2

2. ZPLD I/O pin

3. PE2

3. Latched Address Out – A2

PE3

Port PE, pin 3

Multiple functions

1. PE3

I/O

1. I/O pin

2. PE3

2. ZPLD I/O pin

3. PE3

3. Latched Address Out – A3

PE4

Port PE, pin 4

Multiple functions

1. PE4

I/O

1. I/O pin

2. PE4

2. ZPLD I/O pin

3. PE4

3. Latched Address Out – A4

PE5

Port PE, pin 5

Multiple functions

1. PE5

I/O

1. I/O pin

2. PE5

2. ZPLD I/O pin

3. PE5

3. Latched Address Out – A5

PE6

Port PE, pin 6

Multiple functions

1. PE6

I/O

1. I/O pin

2. PE6

2. ZPLD I/O pin

3. PE6

3. Latched Address Out – A6

PE7

Port PE, pin 7

Multiple functions

1. APD CLK

1. Automatic Power Down Clock Input

2. PE7

I/O

2. I/O pin

3. PE7

3. ZPLD I/O pin

4. PE7

4. Latched Address Out – A7

Vstdby

SRAM power pin for standby

operation (battery backup)

power pin

GND

Ground pin

8.0

Table 2.

PSD4XX Pin

Descriptions

(Cont.)

Available only in PSD4XXA2 and ZPSD4XXA2 Series.

PSD4XX Family

9.0

The PSD4XX

Architecture

PSD4XX consists of five major functional blocks:

ZPLD Blocks

Bus Interface

I/O Ports

Memory Block

Power Management Unit

The functions of each block are described in the following sections. Many of the blocks

perform multiple functions, and are user configurable. The chip configurations are specified

by the user in the PSDsoft Development Software. Other configurations are specified by

setting up the appropriate bits in the configuration registers during run time.

9.1 The ZPLD Block

The PSD4XX series devices provide two ZPLD configurations. The ZPLD in the

PSD4XXA1 devices has 8 registered macrocells, 8 combinatorial macrocells, and up to 113

product terms.

The PSD4XXA2 has a full function ZPLD with 24 registered macrocells and up to 126

product terms.

9.1.1 The PSD4XXA1 ZPLD Block

Key Features

2 Embedded ZPLD devices

8 registered and 8 combinatorial macrocells

Combinatorial/registered outputs

Maximum 113 product terms

Programmable output polarity

User configured register clear/preset

User configured register clock input

37 Inputs

Accessible via 16 I/O pins

Power Saving Mode

UV-Erasable

General Description

The ZPLD block has 2 embedded PLD devices:

DPLD

The Address Decoding PLD, generating select signals to internal I/O or memory blocks.

GPLD

The General Purpose PLD provides 8 registered and combinatorial programmable

macrocells for general or complex logic implementation; dedicated to user application.

Figure 4 shows the architecture of the ZPLD. The PLD devices all share the same input

bus. The true or complement of the 37 input signals are fed to the programmable

AND-ARRAY. Names and sources of the input signals are shown in Table 3. The PB

signals, depending on user configuration, can either be macrocell feedbacks or inputs from

Port B.