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L9904
October 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
s
OPERATING SUPPLY VOLTAGE 8V TO 28V,
OVERVOLTAGE MAX. 40V
s
OPERATING SUPPLY VOLTAGE 6V WITH
IMPLEMENTED STEPUP CONVERTER
s
QUIESCENT CURRENT IN STANDBY MODE
LESS THAN 50µA
s
ISO 9141 COMPATIBLE INTERFACE
s
CHARGE PUMP FOR DRIVING A POWER
MOS AS REVERSE BATTERY PROTECTION
s
PWM OPERATION FREQUENCY UP TO
30KHZ
s
PROGRAMMABLE CROSS CONDUCTION
PROTECTION TIME
s
OVERVOLTAGE, UNDERVOLTAGE, SHORT
CIRCUIT AND THERMAL PROTECTION
s
REAL TIME DIAGNOSTIC
DESCRIPTION
Control circuit for power MOS bridge driver in auto-
motive applications with ISO 9141bus interface.
SO20
ORDERING NUMBER: L9904
PRODUCT PREVIEW
MOTOR BRIDGE CONTROLLER
BLOCK DIAGRAM
VS
DIR
PWM
EN
RX
TX
CP
CB1
GH1
S1
GL1
CB2
GH2
S2
GL2
K
=
PR
VCC
=
=
ISO-Interface
VCC
GND
ST
Ref erence
BIAS
Charge
pump
Co
nt
rol
L
ogi
c
Overvoltage
Undervoltage
PWM
R
DI R
R
RX
R
TX
R
0.5
•
VVS
RS2
RGL2
RGL1
RS1
RCP
REN
VCC
Timer
I KH
V S2TH
Thermal shutdown
V S1TH
DG
VCC
RDG
VSTH
fST
=
-
+
10
1
2
4
5
3
6
7
8
20
9
16
15
17
18
19
14
12
13
11
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L9904
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PIN FUNCTION
PIN CONNECTION (Top view)
N°
Pin
Description
1
ST
Open Drain Switch for Stepup converter
2
DG
Open drain diagnostic output
3
PWM
PWM input for H-bridge control
4
EN
Enable input
5
DIR
Direction select input for H-bridge control
6
PR
Programmable cross conduction protection time
7
RX
ISO 9141 interface, receiver output
8
TX
ISO 9141 interface, transmitter input
9
K
ISO 9141 Interface, bidirectional communication K-line
10
VS
Supply voltage
11
CP
Charge pump for driving a power MOS as reverse battery protection
12
GH1
Gate driver for power MOS highside switch in halfbridge 1
13
CB1
External bootstrap capacitor
14
S1
Source/drain of halfbridge 1
15
GH2
Gate driver for power MOS highside switch in halfbridge 2
16
CB2
External bootstrap capacitor
17
S2
Source/drain of halfbridge 2
18
GL2
Gate driver for power MOS lowside switch in halfbridge 2
19
GL1
Gate driver for power MOS lowside switch in halfbridge 1
20
GND
Ground
ST
DG
PWM
EN
DIR
RX
PR
TX
K
GH1
CB1
S1
CB2
GH2
S2
GL2
GL1
GND
1
3
2
4
5
6
7
8
9
18
17
16
15
14
12
13
11
19
10
20
VS
CP
SO20
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L9904
ABSOLUTE MAXIMUM RATINGS
For externally applied voltages or currents exceeding these limits damage of the device may occur!
All pins of the IC are protected against ESD. The verification is performed according to MIL883C, human body
model with R=1.5k
Ω
, C=100pF and discharge voltage ±2kV, corresponding to a maximum discharge energy of
0.2mJ.
Symbol
Parameter
Value
Unit
V
CB1
, V
CB2
Bootstrap voltage
-0.3 to 40
V
I
CB1
, I
CB2
Bootstrap current
-100
mA
V
CP
Charge pump voltage
-0.3 to 40
V
I
CP
Charge pump current
-1
mA
V
DIR
,V
EN
,V
PWM
,V
TX
Logic input voltage
-0.3 to 7
V
I
DIR
,I
EN
,I
PWM
,I
TX
Logic input current
±1
mA
V
DG
,V
RX
Logic output voltage
-0.3 to 7
V
I
DG
,I
RX
Logic output current
-1
mA
V
GH1
, V
GH2
Gate driver voltage
-0.3 to V
SX
+ 10
V
I
GH1
, I
GH2
Gate driver current
-1
mA
V
GL1
, V
GL2
Gate driver voltage
-0.3 to 10
V
I
GL1
, I
GL2
Gate driver current
-10
mA
V
K
K-line voltage
-20 to V
S
V
V
PR
Programming input voltage
-0.3 to 7
V
I
PR
Programming input current
-1
mA
V
S1
, V
S2
Source/drain voltage
-2 to V
VS
+ 2
V
I
S1
, I
S2
Source/drain current
-10
mA
V
ST
Output voltage
-0.3 to 40
V
I
ST
Step up output current
-1
mA
V
VSDC
DC supply voltage
-0.3 to 28
V
V
VSP
Pulse supply voltage (T < 500ms)
40
V
I
VS
DC supply current
-100
mA
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L9904
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THERMAL DATA
1. see application note 110 for SO packages.
ELECTRICAL CHARACTERISTCS (8V < V
VS
< 20V, V
EN
= HIGH, -40°C
≤
T
J
≤
150°C, unless otherwise spec-
ified. The voltages are refered to GND and currents are assumed positive, when current flows into the pin.
Symbol
Parameter
Value
Unit
T
J
Operating junction temperature
-40 to 150
°C
T
JSD
Junction temperature thermal shutdown threshold
min 150
°C
T
JSDH
Junction thermal shutdown hysteresis
typ 15
°C
R
th j-amb
Thermal resistance junction to ambient
1)
85
°C/W
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Supply (VS)
V
VS OVH
Overvoltage disable HIGH
threshold
28
33
36
V
V
VS OVh
Overvoltage threshold hysteresis
2)
1.6
V
V
VS UVH
Undervoltage disable HIGH
threshold
6
7
V
V
VS UVh
Undervoltage threshold
hysteresis
2)
0.66
V
I
VSL
Supply current
V
EN
= 0 ; V
VS
= 13.5V; T
J
< 85°C
50
µA
I
VSH
Supply current, pwm-mode
V
VS
= 13.5V; V
EN
= HIGH;
V
DIR
= LOW; S1 = S2 = GND
f
PWM
= 20kHz; C
CBX
= 0.1µF;
C
GLX
= 4.7nF; C
GHX
= 4.7nF;
R
PR
= 10k
Ω
; C
PR
= 150pF
8.1
13
mA
I
VSD
Supply current, dc-mode
V
VS
= 13.5V; V
EN
= HIGH;
V
DIR
= LOW; S1 = S2 = GND
V
PWM
= LOW; C
GHX
= 4.7nF
R
PR
= 10k
Ω
; C
PR
= 150pF
5.8
10
mA
Enable input (EN)
V
ENL
Low level
1.5
V
V
ENH
High level
3.5
V
V
ENh
Hysteresis threshold
2)
1
V
R
EN
Input pull down resistance
V
EN
= 5V
16
50
100
k
Ω
H-bridge control inputs (DIR, PWM)
V
DIRL
V
PWML
Input low level
1.5
V
V
DIRH
V
PWMH
Input high level
3.5
V
V
DIRh
V
PWMh
Input threshold hysteresis
2)
1
V
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L9904
R
DIR
R
PWM
Internal pull up resistance
to internal VCC
3)
V
DIR
= 0; V
PWM
= 0
16
50
100
k
Ω
DIAGNOSTIC output (DG)
V
DG
Output drop
I
DG
= 1mA
0.6
V
R
DG
Internal pull up resistance
to internal VCC
3)
V
DG
= 0V
10
20
40
k
Ω
Programmable cross conduction protection
4)
N
PR
Threshold voltage ratio V
PRH
/
V
PRL
R
PR
= 10k
Ω
1.8
2
2.2
I
PR
Current capability
V
PR
= 2V
-0.5
mA
ISO interface, transmission input (TX)
V
TXL
Input low level
1.5
V
V
TXH
Input high level
3.5
V
V
TXh
Input hysteresis voltage 2)
1
V
R
TX
Internal pull up resistance to
internal VCC 3)
V
TX
= 0
10
20
40
k
Ω
ISO interface, receiver output (RX)
V
RXL
Output voltage high stage
TX = HIGH; I
RX
= 0; V
K
= V
VS
4.5
5.5
V
R
RX
Internal pull up resistance
to internal VCC
3)
TX = HIGH;
V
RX
= 0V
5
10
20
k
Ω
R
RXON
ON resistance to ground
TX = LOW;
I
RX
= 1mA
40
90
Ω
t
RXH
Output high delay time
Fig. 1
0.5
µs
t
RXL
Output low delay time
0.5
µs
ISO interface, K-line (K)
V
KL
Input low level
-20V
0.45 ·
V
VS
V
KH
Input high level
0.55 ·
V
VS
V
VS
V
Kh
Input hysteresis voltage 2)
0.025·
V
VS
0.8V
I
KH
Input current
V
TX
= HIGH
-5
25
µA
R
KON
ON resistance to ground
V
TX
= LOW; I
K
=10mA
10
30
Ω
I
KSC
Short circuit current
V
TX
= LOW
40
130
mA
f
K
Transmission frequency
60
100
kHz
2. not tested in production: guaranteed by design and verified in characterization
3. Internal V
VCC
is 4.5V ... 5.5V
4. see page 18 for calculation of programmable cross conduction protection time
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
ELECTRICAL CHARACTERISTICS (continued)
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L9904
6/17
t
Kr
Rise time
V
VS
= 13.5V; Fig. 1
External loads at K-line:
R
K
= 510
Ω
pull up
to V
VS
C
K
= 2.2nF to GND
2
6
µs
t
Kf
Fall time
2
6
µs
t
KH
Switch high delay time
4
17
µs
t
KL
Switch low delay time
4
17
µs
t
SH
Short circuit detection time
V
VS
= 13.5V;
TX = LOW
V
K
> 0.55 · V
VS
10
40
µs
Charge pump
V
CP
Charge pump voltage
V
VS
= 8V
V
VS
= 13.5V
V
VS
= 20V
V
VS
+
7V
V
VS
+
10V
V
VS
+
10V
V
VS
+
14V
V
VS
+
14V
V
VS
+14V
I
CP
Charging current
V
CP
= V
VS
+ 8V
V
VS
= 13.5V
-50
-75
µA
t
CP
Charging time
2)
V
CP
= V
VS
+ 8V
V
VS
= 13.5V
C
CP
= 10nF
1.2
4
ms
f
CP
Charge pump frequency
V
VS
= 13.5V
250
500
750
kHz
Drivers for external highside power MOS
V
CB1
V
CB2
Bootstrap voltage
V
VS
= 8V; I
CBX
= 0; V
SX
= 0
V
VS
=13.5V; I
CBX
= 0; V
SX
= 0
V
VS
= 20V; I
CBX
= 0; V
SX
= 0
7.5
10
10
14
14
14
V
V
V
R
GH1L
R
GH2L
ON-resistance of SINK stage
V
CBX
= 8V; V
SX
= 0
I
GHX
= 50mA; T
J
= 25°C
10
Ω
V
CBX
= 8V; V
SX
= 0
I
GHX
= 50mA; T
J
= 125°C
20
Ω
R
GH1H
R
GH2H
ON-resistance of SOURCE stage
I
GHX
= -50mA; T
J
= 25°C
I
GHX
= -50mA; T
J
= 125°C
10
20
Ω
Ω
V
GH1H
V
GH2H
Gate ON voltage (SOURCE)
V
VS
= V
SX
= 8V; I
GHX
= 0;
C
CBX
= 0.1µF
V
VS
+6.5V
V
VS
+14V
V
VS
= V
SX
= 13.5V; I
GHX
= 0;
C
CBX
= 0.1µF
V
VS
+
10V
V
VS
+14V
V
VS
= V
SX
= 20V; I
GHX
= 0;
C
CBX
= 0.1µF
V
VS
+10V
V
VS
+14V
R
GH1
R
GH2
Gate discharge resistance
EN = LOW
10
100
k
Ω
R
S1
R
S2
Sink resistance
10
100
k
Ω
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
ELECTRICAL CHARACTERISTICS (continued)
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L9904
Drivers for external lowside power MOS
R
GL1L
R
GL2L
ON-resistance of SINK stage
I
GLX
= 50mA; T
J
= 25°C
I
GLX
= 50mA; T
J
= 125°C
10
20
Ω
Ω
R
GL1H,
R
GL2H
ON-resistance of SOURCE stage
I
GLX
= -50mA; T
J
= 25°C
I
GLX
= -50mA; T
J
= 125°C
10
20
Ω
Ω
V
GL1H,
V
GL2H
Gate ON voltage (SOURCE)
V
VS
= 8V; I
GLX
= 0
V
VS
= 13.5V; I
GLX
= 0
V
VS
= 20V; I
GLX
= 0
7V
10V
10V
V
VS
V
VS
14V
R
GL1
R
GL2
Gate discharge resistance
EN = LOW
10
100
k
Ω
2. not tested in production: guaranteed by design and verified in characterization
Timing of the drivers
t
GH1LH
t
GH2LH
Propagation delay time
Fig. 2
V
VS
= 13.5V
V
S1
= V
S2
=0
C
CBX
= 0.1µF
RPR= 10kW
500
ns
t
GH1LH
t
GH2LH
Propagation delay time including
cross conduction protection time
t
CCP
Fig. 2
V
VS
= 13.5V
V
S1
= V
S2
=0
C
CBX
= 0.1µF
C
PR
= 150pF;
R
PR
= 10k
Ω
;
5)
0.7
1
1.3
µs
t
GH1HL
t
GH2HL
Propagation delay time
500
ns
t
GL1LH
t
GL2LH
Propagation delay time
Fig. 2
V
VS
= 13.5V
V
S1
= V
S2
=0
C
CBX</