1/33
L6917B
September 2002
s
2 PHASE OPERATION WITH
SYNCRHONOUS RECTIFIER CONTROL
s
ULTRA FAST LOAD TRANSIENT RESPONSE
s
INTEGRATED HIGH CURRENT GATE
DRIVERS: UP TO 2A GATE CURRENT
s
TTL-COMPATIBLE 5 BIT PROGRAMMABLE
OUTPUT COMPLIANT WITH VRM 9.0
s
0.8% INTERNAL REFERENCE ACCURACY
s
10% ACTIVE CURRENT SHARING
ACCURACY
s
DIGITAL 2048 STEP SOFT-START
s
OVERVOLTAGE PROTECTION
s
OVERCURRENT PROTECTION REALIZED
USING THE LOWER MOSFET'S R
dsON
OR A
SENSE RESISTOR
s
300 kHz INTERNAL OSCILLATOR
s
OSCILLATOR EXTERNALLY ADJUSTABLE
UP TO 600kHz
s
POWER GOOD OUTPUT AND INHIBIT
FUNCTION
s
REMOTE SENSE BUFFER
s
PACKAGE: SO-28
APPLICATIONS
s
POWER SUPPLY FOR SERVERS AND
WORKSTATIONS
s
POWER SUPPLY FOR HIGH CURRENT
MICROPROCESSORS
s
DISTRIBUTED DC-DC CONVERTERS
DESCRIPTION
The device is a power supply controller specifically
designed to provide a high performance DC/DC con-
version for high current microprocessors.
The device implements a dual-phase step-down con-
troller with a 180° phase-shift between each phase.
A precise 5-bit digital to analog converter (DAC) al-
lows adjusting the output voltage from 1.100V to
1.850V with 25mV binary steps.
The high precision internal reference assures the se-
lected output voltage to be within ±0.8%. The high
peak current gate drive affords to have fast switching
to the external power mos providing low switching
losses.
The device assures a fast protection against load
over current and load over/under voltage. An internal
crowbar is provided turning on the low side mosfet if
an over-voltage is detected. In case of over-current,
the system works in Constant Current mode.
SO-28
ORDERING NUMBERS:L6917BD
L6917BDTR (Tape & Reel)
5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER
BLOCK DIAGRAM
CURRENT
READING
CURRENT
READING
IFB
TOTAL
CURRENT
AVG
CURRENT
CH 1 OVER
CURRENT
CH 2 OVER
CURRENT
DAC
DIGITAL
SOFT START
L
OGI
C
P
W
M
AD
AP
T
IVE AN
T
I
CRO
S
S
-C
O
NDUCT
IO
N
L
OGI
C
P
W
M
AD
AP
T
IVE AN
T
I
CRO
S
S
-C
O
NDUCT
IO
N
CH1 OVER
CURRENT
CH2 OVER
CURRENT
LOGIC
AND
PROTECTIONS
2 PHASE
OSCILLATOR
PWM1
CU
RR
E
N
T
CO
R
R
E
C
T
IO
N
PWM2
CU
RR
E
N
T
CO
R
R
E
C
T
IO
N
ERROR
AMPLIFIER
REMOTE
BUFFER
10k
10k
10k
LS
LS
HS
Vcc
HS
BOOT1
UGATE1
PHASE1
LGATE1
ISEN1
PGNDS1
PGND
PGNDS2
ISEN2
LGATE2
PHASE2
UGATE2
BOOT2
Vcc
COMP
FB
VSEN
FBG
FBR
VID0
VID1
VID2
VID3
VID4
PGOOD
ROSC / INH
SGND
VCCDR
10k
< >
+
-
+
+
-
VCCDR
VCC
L6917B
2/33
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
PIN CONNECTION
Symbol
Parameter
Value
Unit
Vcc, V
CCDR
to PGND
15
V
V
BOOT
-V
PHASE
Boot Voltage
15
V
V
UGATE1
-V
PHASE1
V
UGATE2
-V
PHASE2
15
V
LGATE1, PHASE1, LGATE2, PHASE2 to PGND
-0.3 to Vcc+0.3
V
All other pins to PGND
-0.3 to 7
V
V
phase
Sustainable Peak Voltage t < 20ns @ 600kHz
26
V
Symbol
Parameter
Value
Unit
R
th j-amb
Thermal Resistance Junction to Ambient
60
°
C/W
T
max
Maximum junction temperature
150
°
C
T
storage
Storage temperature range
-40 to 150
°
C
T
j
Junction Temperature Range
-25 to 125
°C
P
MAX
Max power dissipation at T
amb
= 25°C
2
W
LGATE1
VCCDR
PHASE1
VID3
VID2
VID1
FB
BOOT1
UGATE1
VID4
BOOT2
PGOOD
UGATE2
PHASE2
LGATE2
PGND
1
3
2
4
5
6
7
8
9
18
17
16
15
19
20
10
VSEN
VCC
GND
COMP
SO28
11
12
13
14
24
23
22
21
25
26
27
28
FBG
ISEN1
PGNDS1
FBR
OSC / INH / FAULT
ISEN2
PGNDS2
VID0
3/33
L6917B
ELECTRICAL CHARACTERISTICS
V
CC
= 12V ±10%, T
J
= 0 to 70°C unless otherwise specified
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
Vcc SUPPLY CURRENT
I
CC
Vcc supply current
HGATEx and LGATEx open
V
CCDR
=V
BOOT
=12V
7.5
10
12.5
mA
I
CCDR
V
CCDR
supply current
LGATEx open; V
CCDR
=12V
2
3
4
mA
I
BOOTx
Boot supply current
HGATEx open; PHASEx to PGND
V
CC
=V
BOOT
=12V
0.5
1
1.5
mA
POWER-ON
Turn-On V
CC
threshold
V
CC
Rising; V
CCDR
=5V
7.8
9
10.2
V
Turn-Off V
CC
threshold
V
CC
Falling; V
CCDR
=5V
6.5
7.5
8.5
V
Turn-On V
CCDR
Threshold
V
CCDR
Rising
V
CC
=12V
4.2
4.4
4.6
V
Turn-Off V
CCDR
Threshold
V
CCDR
Falling
V
CC
=12V
4.0
4.2
4.4
V
OSCILLATOR/INHIBIT/FAULT
f
OSC
Initial Accuracy
OSC = OPEN
OSC = OPEN; Tj=0
°
C to 125
°
C
278
270
300
322
330
kHz
kHz
f
OSC,Rosc
Total Accuracy
R
T
to GND=74k
Ω
450
500
550
kHz
INH
Inhibit threshold
I
SINK
=5mA
0.8
0.85
0.9
V
d
MAX
Maximum duty cycle
OSC = OPEN
70
75
%
∆
Vosc
Ramp Amplitude
1.8
2
2.2
V
FAULT
Voltage at pin OSC
OVP or UVP Active
4.75
5.0
5.25
V
REFERENCE AND DAC
Output Voltage
Accuracy
VID0, VID1, VID2, VID3, VID4
see Table1;
FBR = V
OUT
; FBG = GND
-0.8
-
0.8
%
I
DAC
VID pull-up Current
VIDx = GND
4
5
6
µ
A
VID pull-up Voltage
VIDx = OPEN
3.1
-
3.4
V
ERROR AMPLIFIER
DC Gain
80
dB
SR
Slew-Rate
COMP=10pF
15
V/
µ
s
DIFFERENTIAL AMPLIFIER (REMOTE BUFFER)
DC Gain
1
V/V
CMRR
Common Mode Rejection Ratio
40
dB
L6917B
4/33
Input Offset
FBR=1.100V to1.850V;
FBG=GND
-12
12
mV
SR
Slew Rate
VSEN=10pF
15
V/
µ
s
DIFFERENTIAL CURRENT SENSING
I
ISEN1
,
I
ISEN2
Bias Current
Iload=0
45
50
55
µ
A
I
PGNDSx
Bias Current
45
50
55
µ
A
I
ISEN1
,
I
ISEN2
Bias Current at
Over Current Threshold
80
85
90
µ
A
I
FB
Active Droop Current
Iload<0%
Iload=100%
47.5
0
50
1
52.5
µ
A
µ
A
GATE DRIVERS
t
RISE
HGATE
High Side
Rise Time
V
BOOTx
-V
PHASEx
=10V;
C
HGATEx
to PHASEx=3.3nF
15
30
ns
I
HGATEx
High Side
Source Current
V
BOOTx
-V
PHASEx
=10V 2
A
R
HGATEx
High Side
Sink Resistance
V
BOOTx
-V
PHASEx
=12V;
1.5
2
2.5
Ω
t
RISE
LGATE
Low Side
Rise Time
V
CCDR
=10V;
C
LGATEx
to PGNDx=5.6nF
30
55
ns
I
LGATEx
Low Side
Source Current
V
CCDR
=10V
1.8
A
R
LGATEx
Low Side
Sink Resistance
V
CCDR
=12V
0.7
1.1
1.5
Ω
P GOOD and OVP/UVP PROTECTIONS
PGOOD
Upper Threshold
(V
SEN
/DACOUT)
V
SEN
Rising
108
112
116
%
PGOOD
Lower Threshold
(V
SEN
/DACOUT)
V
SEN
Falling
84
88
92
%
OVP
Over Voltage Threshold
(V
SEN
)
V
SEN
Rising
2.0
2.25
V
UVP
Under Voltage Trip
(V
SEN
/DACOUT)
V
SEN
Falling
56
60
64
%
V
PGOOD
PGOOD Voltage Low
I
PGOOD
= -4mA
0.3
0.4
0.5
V
ELECTRICAL CHARACTERISTICS (continued)
V
CC
= 12V ±10%, T
J
= 0 to 70°C unless otherwise specified
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
5/33
L6917B
Table 1. VID Settings
VID4
VID3
VID2
VID1
VID0
Output Voltage (V)
1
1
1
1
1
OUTPUT OFF
1
1
1
1
0
1.100
1
1
1
0
1
1.125
1
1
1
0
0
1.150
1
1
0
1
1
1.175
1
1
0
1
0
1.200
1
1
0
0
1
1.225
1
1
0
0
0
1.250
1
0
1
1
1
1.275
1
0
1
1
0
1.300
1
0
1
0
1
1.325
1
0
1
0
0
1.350
1
0
0
1
1
1.375
1
0
0
1
0
1.400
1
0
0
0
1
1.425
1
0
0
0
0
1.450
0
1
1
1
1
1.475
0
1
1
1
0
1.500
0
1
1
0
1
1.525
0
1
1
0
0
1.550
0
1
0
1
1
1.575
0
1
0
1
0
1.600
0
1
0
0
1
1.625
0
1
0
0
0
1.650
0
0
1
1
1
1.675
0
0
1
1
0
1.700
0
0
1
0
1
1.725
0
0
1
0
0
1.750
0
0
0
1
1
1.775
0
0
0
1
0
1.800
0
0
0
0
1
1.825
0
0
0
0
0
1.850
L6917B
6/33
PIN FUNCTION
N
Name
Description
1
LGATE1
Channel 1 low side gate driver output.
2
VCCDR
Mosfet driver supply. It can be varied from 5V to 12V.
3
PHASE1 This pin is connected to the source of the upper mosfet and provides the return path for the high
side driver of channel 1.
4
UGATE1 Channel 1 high side gate driver output.
5
BOOT1
Channel 1 bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper
mosfet. Connect through a capacitor to the PHASE1 pin and through a diode to Vcc (cathode vs.
boot).
6
VCC
Device supply voltage. The operative supply voltage is 12V.
7
GND
All the internal references are referred to this pin. Connect it to the PCB signal ground.
8
COMP
This pin is connected to the error amplifier output and is used to compensate the control
feedback loop.
9
FB
This pin is connected to the error amplifier inverting input and is used to compensate the voltage
control feedback loop.
A current proportional to the sum of the current sensed in both channel is sourced from this pin
(50
µ
A at full load, 70
µ
A at the Over Current threshold). Connecting a resistor between this pin
and VSEN pin allows programming the droop effect.
10
VSEN
Connected to the output voltage it is able to manage Over & Under-voltage conditions and the
PGOOD signal. It is internally connected with the output of the Remote Sense Buffer for Remote
Sense of the regulated voltage.
If no Remote Sense is implemented, connect it directly to the regulated voltage in order to
manage OVP, UVP and PGOOD.
11
FBR
Remote sense buffer non-inverting input. It has to be connected to the positive side of the load to
perform a remote sense.
If no remote sense is implemented, connect directly to the output voltage (in this case connect
also the VSEN pin directly to the output regulated voltage).
12
FBG
Remote sense buffer inverting input. It has to be connected to the negative side of the load to
perform a remote sense.
Pull-down to ground if no remote sense is implemented.
13
ISEN1
Channel 1 current sense pin. The output current may be sensed across a sense resistor or
across the low-side mosfet Rds
ON.
This pin has to be connected to the low-side mosfet drain or
to the sense resistor through a resistor Rg in order to program the positive current limit at 140%
as follow:
Where 35
µ
A is the current offset information relative to the Over Current condition (offset at OC
threshold minus offset at zero load).
The net connecting the pin to the sense point must be routed as close as possible to the
PGNDS1 net in order to couple in common mode any picked-up noise.
14
PGNDS1 Channel 1 Power Ground sense pin. The net connecting the pin to the sense point (*) must be
routed as close as possible to the ISEN1 net in order to couple in common mode any picked-up
noise.
15
PGNDS2 Channel 2 Power Ground sense pin. The net connecting the pin to the sense point (*) must be
routed as close as possible to the ISEN2 net in order to couple in common mode any picked-up
noise.
I
M A X
35
µ
A R
g
⋅
R
se nse
--------------------------
=
(*) Through a resistor Rg.
7/33
L6917B
16
ISEN2
Channel 2 current sense pin. The output current may be sensed across a sense resistor or
across the low-side mosfet Rds
ON.
This pin has to be connected to the low-side mosfet drain or
to the sense resistor through a resistor Rg in order to program the positive current limit at 140%
as follow:
Where 35
µ
A is the current offset information relative to the Over Current condition (offset at OC
threshold minus offset at zero load).
The net connecting the pin to the sense point must be routed as close as possible to the
PGNDS2 net in order to couple in common mode any picked-up noise.
17
OSC/
INH/
FAULT
Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the
external frequency is increased according to the equation:
Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according to
the equation:
If the pin is not connected, the switching frequency is 300KHz.
Forcing the pin to a voltage lower than 0.8V, the device stop operation and enter the inhibit state.
The pin is forced high when an over or under voltage is detected. This condition is latched; to
recover it is necessary turn off and on VCC.
18-22
VID4-0
Voltage IDentification pins. These input are internally pulled-up and TTL compatible. They are
used to program the output voltage as specified in Table 1 and to set the power good thresholds.
Connect to GND to program a ‘0’ while leave floating to program a ‘1’.
23
PGOOD
This pin is an open collector output and is pulled low if the output voltage is not within the above
specified thresholds.
If not used may be left floating.
24
BOOT2
Channel 2 bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper
mosfet. Connect through a capacitor to the PHASE2 pin and through a diode to Vcc (cathode vs.
boot).
25
UGATE2 Channel 2 high side gate driver output.
26
PHASE2 This pin is connected to the source of the upper mosfet and provides the return path for the high
side driver of channel 2.
27
LGATE2
Channel 2 low side gate driver output.
28
PGND
Power ground pin. This pin is common to both sections and it must be connected through the
closest path to the low side mosfets source pins in order to reduce the noise injection into the
device.
PIN FUNCTION (continued)
N
Name
Description
I
M A X
35
µ
A R
g
⋅
R
se nse
--------------------------
=
f
S
300KHz
14.82 10
6
⋅
R
O SC
K
Ω
(
)
-----------------------------
+
=
f
S
300KHz
12.91 10
7
⋅
R
O SC
K
Ω
(
)
-----------------------------
–
=
L6917B
8/33
Device Description
The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections
for a high performance dual-phase step-down DC-DC converter optimized for microprocessor power supply. It
is designed to drive N Channel MOSFETs in a dual-phase synchronous-rectified buck topology. A 180 deg
phase shift is provided between the two phases allowing reduction in the input capacitor current ripple, reducing
also the size and the losses. The output voltage of the converter can be precisely regulated, programming the
VID pins, from 1.100V to 1.850V with 25mV binary steps, with a maximum tolerance of ±0.8% over temperature
and line voltage variations. The device provides an average current-mode control with fast transient response.
It includes a 300kHz free-running oscillator adjustable up to 600kHz. The error amplifier features a 15V/
µ
s slew
rate that permits high converter bandwidth for fast transient performances. Current information is read across
the lower mosfets r
DSON
or across a sense resistor in fully differential mode. The current information corrects
the PWM output in order to equalize the average current carried by each phase. Current sharing between the
two phases is then limited at ±10% over static and dynamic conditions. The device protects against over-cur-
rent, with an OC threshold for each phase, entering in constant current mode. Since the current is read across
the low side mosfets, the constant current keeps constant the bottom of the inductors current triangular wave-
form. When an under voltage is detected the device latches and the FAULT pin is driven high. The device per-
forms also over voltage protection that disable immediately the device turning ON the lower driver and driving
high the FAULT pin.
Oscillator
The device has been designed in order to operate an each phase at the same switching frequency of the internal
oscillator. So, input and output resulting frequency is doubled.
The switching frequency is internally fixed to 300kHz. The internal oscillator generates the triangular waveform
for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the
oscillator is typically 25
µ
A and may be varied using an external resistor (R
OSC
) connected between OSC pin
and GND or Vcc. Since the OSC pin is maintained at fixed voltage (typ). 1.235V, the frequency is varied pro-
portionally to the current sunk (forced) from (into) the pin considering the internal gain of 12KHz/
µ
A.
In particular connecting it to GND the frequency is increased (current is sunk from the pin), while connecting ROSC
to Vcc=12V the frequency is reduced (current is forced into the pin), according to the following relationships:
Note that forcing a 25
µ
A current into this pin, the device stops switching because no current is delivered to the