www.fairchildsemi.com
REV. 1.1.3 2/20/03
Features
• Sinks and sources 2.1A continuous, 3A peak
• 0 to +125°C operating temperature range
• 5mA Buffered VREFOUT = VDDQ/2
• Load regulation: VTT = VREFOUT ± 40mV
• On-chip thermal limiting
• Low Cost SO-14, Power Enhanced eTSSOP or
8-pin 5x6mm MLP packages
• Low-Current Shutdown Mode
• Output Short Circuit Protection
Applications
• DDR Terminator VTT supply
Description
The FAN1655 is a low-cost bi-directional LDO specifically
designed for terminating DDR memory bus. It can both sink
and source up to 2.1A continuous, 3A peak, providing
enough current for most DDR applications. Load regulation
meets the JEDEC spec, VTT = VREFOUT ± 40mV.
The FAN1655 includes a buffered reference voltage capable
of supplying up to 5mA current. On-chip thermal limiting
provides protection against a combination of power overload
and ambient temperature that would create an excessive
junction temperature. A shutdown input puts the FAN1655
into a low power mode.
The FAN1655 regulator is available in a power-enhanced
eTSSOP™-16 package, and the standard SOIC-14
Block Diagram
VSS
VSS
VSS
+
-
VTTSENSE
VTTFORCE
VTTFORCE
+
-
VDD
VDD
VDD
SHDN
VDDQ
200k
200k
FAN1655
VSSQ
VREFIN
VREFOUT
FAN1655
3A DDR Bus Termination Regulator
PRODUCT SPECIFICATION
FAN1655
2
REV. 1.1.3 2/20/03
Pin Assignments
Pin Definitions
Typical Application
Pin
Pin Name
Pin Function Description
MLP
eTSSOP
SOIC-14
1, 4
1, 2, 7
1, 2, 7
VDD
Input power for the LDO.
2, 3
3, 6
3, 6
VTTFORCE
The VTT output voltage.
PAD
4, 5, 8
4, 5, 8
VSS
IC Ground.
5
10
9
VTTSENSE
Feedback for remote sense of the VTT voltage.
11
10
VREFIN
Alternative input for direct control of VTTOUT and
VREFOUT.
6
12
11
SHDN
Shutdown. This active low shutdown turns off both VTT
and VREFOUT. This pin has an internal pull-down, and
must be externally driven high for the IC to be on.
13
12
VSSQ
Signal Ground.
7
14
13
VREFOUT
Buffered Voltage Reference Output.
8
15
14
VDDQ
VDDQ Input. Attach this pin to the VDDQ supply to
generate VTT and VREFOUT.
9, 16
NC
No Internal Connection
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
FAN1655
NC
VDDQ
VREFOUT
VSSQ
SHDN
VREFIN
VTTSENSE
NC
VDD
VDD
VTTFORCE
VSS
VSS
VTTFORCE
VDD
VSS
14
13
12
11
10
9
8
1
2
3
4
5
6
7
FAN1655M
VDDQ
VREFOUT
VSSQ
SHDN
VREFIN
VTTSENSE
VSS
VDD
VDD
VTTFORCE
VSS
VSS
VTTFORCE
VDD
VDDQ
VREFOUT
SHDN
VTTSENSE
VDD
VTTFORCE
VTTFORCE
VDD
GND
1
2
3
4
8
7
6
5
16-Lead Plastic eTSSOP-16
θ
JC
= 4˚C/W*
*With package power slug soldered to 0.5
square inch copper area over backside
ground plane of internal power plane
14-Lead Plastic SOIC
θ
JC
= 37˚C/W,
θ
JA
= 88˚C/W
8-Lead MLP Package (5x6mm)
θ
JC
= 4˚C/W,
θ
JA
= 34˚C/W as
measured on FAN1655MP
Eval Board
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
100
µ
F
6V
10
µ
F
GND
VDD
1nF
(connect to VTTFORCE
at the load)
VTTSENSE
470
µ
F
10
µ
F
VTTFORCE
1nF
GND
VREFOUT
SHDN
VDDQ
10k
FAN1655
Figure 1. (eTSSOP pinout shown)
FAN1655
PRODUCT SPECIFICATION
REV. 1.1.3 2/20/03
3
1.240
1.245
1.250
1.255
1.260
-3000
-2000
-1000
0
1000
2000
3000
V
TT
Load Current (mA)
V
TT
OUTPUT (V)
-40
-20
0
20
40
60
80
Quiescent Current vs. Temperature
QUIESCENT CURRENT (mA)
AMBIENT TEMPERATURE
(˚C)
4.5
3
0
1.5
-60
100
120
140
6
7.5
9
-5
-4
-3
-2
-1
0
1
V
REF
Output Change vs. I
REF
∆
V
REFOUT
(mV)
V
REF
LOAD CURRENT (mA)
0.5
0
-1.0
-0.5
-6
2
3
4
1.0
5
6
V
DD
= V
DDQ
= 2.5V
T
A
= 25˚C
1.0
10.0
100.0
1
1.5
2
2.5
3
Peak Load Current (A)
Current Pulse Duration (S)
T
A
=25
°
C
T
A
=70
°
C
Figure 2. Quiescent Current vs.
Ambient Temperature
Figure 3. Reference Output
Load Regulation
Figure 4. V
TT
Load Regulation
Typical Performance Characteristics
Figure 5. Maximum Non-Repetitive Output
Current vs. Pulse Width
(FAN1655M SO-14 Package)
PRODUCT SPECIFICATION
FAN1655
4
REV. 1.1.3 2/20/03
Absolute Maximum Ratings
Recommended Operating Conditions
Electrical Characteristics
(VDD = VDDQ = 2.5V ± 0.2V, and T
A
= 25˚C using circuit in Figure 1, unless otherwise noted.)
The • denotes specifications which apply over the specified operating temperature range.
Supply Voltage VDD, VDDQ
6V
Junction Temperature, T
J
150˚C
Storage Temperature
-65 to 150˚C
Lead Soldering Temperature, 10 seconds
300˚C
Power Dissipation, P
D
FAN1655M (SOIC-14)
1.4W
FAN1655MTF (e-TSSOP)
FAN1655MP (MLP)
See “Power Dissipation
and Derating”
Parameter
Conditions
Min.
Typ.
Max.
Units
Supply Voltage VDD
2.3
2.5
3.6
V
Supply Voltage VDDQ
2.2
2.5
3.0
V
Ambient Operating Temperature
0
125
˚C
VREFIN
1.1
1.25
1.5
V
Parameter
Conditions
Min.
Typ.
Max.
Units
VTT Output Voltage
I
OUT
= 0A, VREFIN = open
VDDQ = 2.3V
VDDQ = 2.5V
VDDQ = 2.7V
I
OUT
= ±2.1A, VREFIN = open
VDDQ = 2.3V
VDDQ = 2.5V
VDDQ = 2.7V
•
•
•
1.135
1.235
1.335
1.110
1.210
1.310
1.150
1.250
1.350
1.150
1.250
1.350
1.165
1.265
1.365
1.190
1.290
1.390
V
V
V
V
V
V
VTT Output Slew Rate
Cload = 10µF
0.3
V/µS
VTT Leakage Current
SHDN = 0V
•
-50
50
µA
VTT Current Limit
±3.1
A
VREFIN Input Impedance
100
K
Ω
VREFOUT Output Voltage
No load
VREFIN = 1.150V
VREFIN = 1.250V
VREFIN = 1.350V
•
•
•
1.145
1.245
1.345
1.150
1.250
1.350
1.155
1.255
1.355
V
V
V
VREFOUT Output Current
VDDQ = 2.3V
•
-5
5
mA
VREFOUT Leakage Current
SHDN = 0V
•
-10
10
µA
SHDN Logic High
•
1.667
V
SHDN Logic Low
•
0.800
V
IDD Supply Current
No load, SHDN = 2.7V
•
7.5
20
mA
VDDQ Leakage Current
SHDN = 0V
•
6
10
µA
VDD Leakage Current
SHDN = 0V
•
3
50
µA
SHDN Input Current
SHDN = 2.7V
•
50
75
µA
Over-Temperature Shutdown
155
˚C
Over-Temperature Hysteresis
30
˚C
FAN1655
PRODUCT SPECIFICATION
REV. 1.1.3 2/20/03
5
Applications Information
Output Capacitor selection
The JEDEC specification for DDR termination requires that
VTT stay within ±40mV of VREF, which must track
VDDQ/2 within 1%. During the initial load transient, the
output capacitor keeps the output within spec. To stay within
the 40mV window, the “load step” due to the load transient
current dropping across the output capacitor’s ESR should be
kept to around 25mV: where ESR <
is given in m
Ω
, and
∆
I is the maximum load current.
For example, to handle a 3A maximum load transient, the
ESR should be no greater than 8m
Ω
. Furthermore, the output
capacitor must be able to hold the load in spec while the
regulator recovers (about 15µS). A minimum value of 470µF
is recommended.
These requirements can be achieved by a combination of
capacitors. FAN1655 requires a minimum of 5m
Ω
of ESR
in the output and is not stable with all-ceramic output
capacitors.
Power Dissipation and Derating
The maximum output current (sink or source) for a 1.25V
output is:
where P
D(MAX)
is the maximum power dissipation which is:
where T
J(MAX)
is the maximum die temperature of the IC
and T
A
is the operating ambient temperature.
FAN1655 has an internal thermal limit at 150°C, which
defines T
J(MAX)
. For the SOIC-14 package,
θ
JA
is given at
88°C/W. Using equation 2, the maximum dissipation at
T
A
= 25°C is 1.4W, which is its rated maximum dissipation.
The e-TSSOP or MLP package, however, use the PCB
copper to cool the IC through the thermal pad on the package
bottom. For maximum dissipation, this pad should be
soldered to the PCB copper, with as much copper area as
possible surrounding it to cool the package. Thermal vias
should be placed as close to the thermal pad as possible to
transfer heat to other layers of copper on the PCB. With large
areas of PCB copper for heat sinking, a
θ
JA
of under 40°C/W
can easily be achieved.
25
∆
I
------
I
OUT MAX
(
)
P
D MAX
(
)
1.25
----------------------
=
(1)
P
D MAX
(
)
T
J MAX
(
)
T
A
–
θ
JA
----------------------------------
=
(2)
PRODUCT SPECIFICATION
FAN1655
6
REV. 1.1.3 2/20/03
Mechanical Dimensions
16 Lead eTSSOP
6.4
5.0
±
0.1
0.10 TYP
4.4
±
0.1
7.72
4.16
3.40
4.00
(1.78)
0.42 TYP
0.65 TYP
1.7 MIN
1.5 MIN
0.25
SEATING PLANE
SEE DETAIL A
DETAIL A
(1.00)
0.75
0.45
GAGE PLANE
LAND PATTERN RECOMMENDATION
0
°
–8
°
R0.09MIN
12
°
TOP & BOTTOM
-A-
-B-
0.65 TYP
0.10
C B A
M
-C-
3.2
(0.90)
+0.15
–0.10
(0.09–0.20)
(0.19–0.30)
0.10
±
0.05 TYP
1.2 MAX
PIN #1 IDENT.
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION ABT,
DATED
10/97.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND THE BAR EXTENSIONS.
D. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994.
BOTTOM VIEW
0.2
ALL LEAD TIPS
ALL LEAD TIPS
C B A
0.1
1
8
1
1
8
8
9
16
9
9
16
16
C
PRODUCT SPECIFICATION
FAN1655
7
REV. 1.1.3 2/20/03
Mechanical Dimensions
14-Lead SOIC
S8.71-8.51;
S1.27-0.40;
S8˚-0˚
S0.50-0.25;X45˚
S1.75-1.35;
S0.25-0.10;z
7.62
S6.20-5.80;
1.27
S0.51-0.35;
S4.00-3.80
7
6
5
4
3
2
1
14
13
12
11
10
9
8
S0.25-0.19;
SEATING PLANE
0.50
1.00
1.27
7.62
LAND PATTERN RECOMMENDATION
5.75
NOTES:
1. This package conforms to JEDEC MS-012, variation AB, ISSUEC dated May, 1990.
2. All dimensions are in millimeters
3. Standard lead finished
200 microinches / 5.08 microns min.
Lead/Tin (solder) oncopper
PRODUCT SPECIFICATION
FAN1655
8
REV. 1.1.3 2/20/03
Mechanical Dimensions
5mmX6mm 8-Lead MLP
NOTES:
B)
DIMENSIONS ARE IN MILLIMETERS.
A)
DOES NOT FULLY CONFORM TO JEDEC
REGISTRATION MO-229, DATED 11/2001.
C)
DIMENSIONING AND TOLERANCES PER
ASME
Y14.5–1994.
LAND PATTERN RECOMMENDATION
TOP VIEW
SIDE VIEW
BOTTOM VIEW
3.81
1.27
PIN #1 IDENT.
(OPTIONAL)
1.27 TYP
0.65 TYP
(1.00)
3.50
4.50
4.25
6.25
1.0 MAX
C
C
C
M C
M
0.10
0.10
0.08
0.05
C
A B
0.05
0.00
0.28–0.40
4.25
1.75
3.25
1.25
0.75
0.35
SEATING
PLANE
A
A
A
A
A
1
2
3
4
8
7
6
5
(0.25)
6.0
B
A
5.0
0.25
2X
C
0.25
2X
C
PRODUCT SPECIFICATION
FAN1655
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
2/20/03 0.0m 004
Stock#DS30004854
2003 Fairchild Semiconductor Corporation
Ordering Information
Part Number
Temperature Range
Package
Packing
FAN1655M
0°C to 125°C
SOIC-14 Rails
FAN1655MX
0°C to 125°C
SOIC-14
Tape and Reel
FAN1655MTF
0°C to 125°C
eTSSOP-16
Rails
FAN1655MTFX
0°C to 125°C
eTSSOP-16
Tape and Reel
FAN1655MPX
0°C to 125°C
MLP-08
Tape and Reel
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.