www.fairchildsemi.com
REV. 1.1.8 10/31/00
Features
• Rectangular-to-Polar or Polar-to-Rectangular conversion
at guaranteed 40 MOPS pipelined throughput rate
• Polar data: 16-bit magnitude, 32-bit input/16-bit output
phase
• 16-bit user selectable two’s complement or sign-and-
magnitude rectangular data formats
• Input register clock enables and asynchronous output
enables simplify interfacing
• User-configurable phase accumulator for waveform
synthesis and amplitude, frequency, or phase modulation
• Magnitude output data overflow flag (in Polar-to-
Rectangular mode)
• Low power consumption CMOS process
• Single +5V power supply
• Available in a 120-pin plastic pin grid array package
(PPGA), 120-pin ceramic pin grid array package (CPGA),
120-pin MQFP to PPGA (MPGA) package, and 120-pin
metric quad flatpack package (MQFP)
Applications
• Scan conversion (phased array to raster)
• Vector magnitude estimation
• Range and bearing derivation
• Spectral analysis
• Digital waveform synthesis, including quadrature
functions
• Digital modulation and demodulation
Description
The TMC2330A VLSI circuit converts bidirectionally
between Cartesian (real and imaginary) and Polar (magnitude
and phase) coordinates at up to 40 MOPS (Million Operations
Per Second).
In its Rectangular-to-Polar mode, the TMC2330A can extract
phase and magnitude information or backward “map” from a
rectangular raster display to a radial (e.g., range-and-azimuth)
data set.
The Polar-to-Rectangular mode executes direct digital waveform
synthesis and modulation. The TMC2330A greatly simplifies
real-time image-space conversion between the radially-generated
image scan data found in radar, sonar, and medical imaging
systems, and raster display formats.
All input and output data ports are registered, and a new trans-
formed data word pair is available at the output every clock
cycle. The user-configurable phase accumulator structure,
input clock enables, and asynchronous three-state output bus
enables simplify interfacing. All signals are TTL compatible.
Fabricated in a submicron CMOS process, the TMC2330A
operates at up to the 40 MHz maximum clock rate over the full
commercial (0 to 70°C) temperature and supply voltage ranges,
and is available in 120-pin plastic pin grid array, 120-pin
ceramic pin grid array, 120-pin metric quad flatpack to PPGA
package, and 120-pin metric quad flatpack packages.
Logic Symbol
TMC2330A
DATA
INPUTS
YPIN
31-0
32
ACC
1-0
CONFIGURATION
CONTROLS
16
OEPY
PYOUT
15-0
OVF
RXOUT
15-0
DATA
OUTPUTS
ENXR
16
TCXY
RTP
CLK
OERX
ENYP
1-0
XRIN
15-0
2
16
TMC2330A
Coordinate Transformer
16 x 16 Bit, 40 MOPS
PRODUCT SPECIFICATION
TMC2330A
2
REV. 1.1.8 10/31/00
Block Diagram
1
XRIN
15-0
ENXR
16
2
AM
TCXY
3
4-21
22
22
22
4-21
16
16
16
16
16
OVF
PYOUT
15-0
OEPY
RXOUT
15-0
16
RPT
TRANSFORMATION PROCESS
16
2
3
16
OERX
ACC
1
ENYP
1-0
C
M
32
32
YPIN
31-0
2
ACC
0
32
32
32
FM
PM
32
32
32
Functional Description
The TMC2330A converts between Rectangular (Cartesian)
and Polar (Phase and Magnitude) coordinate data word pairs.
The user selects the numeric format and transformation to be
performed (Rectangular-To-Polar or Polar-To-Rectangular),
and the operation is performed on the data presented to the
inputs on the next clock. The transformed result is then
available at the outputs 22 clock cycles later, with new out-
put data available every 20ns with a 40 MHz clock. All input
and output data ports are registered, with input clock enables
and asynchronous high-impedance output enables to sim-
plify connections to system buses.
When executing a Rectangular-To-Polar conversion, the input
ports accept 16-bit Rectangular coordinate words, and the out-
put ports generate 16-bit magnitude and 16-bit phase data. The
user selects either two’s complement or sign-and-magnitude
Cartesian data format. Polar magnitude data are always in
magnitude format only. Since the phase angle word is modulo
2
π
, it may be regarded as either unsigned or two’s complement
format (Tables 1 and 2)
.
In Polar-To-Rectangular mode, the input ports accept 16-bit
Polar magnitude and 32-bit phase data, and the output ports
produce 16-bit Rectangular data words. Again, the user
selects between two’s complement or sign-and-magnitude
Cartesian data format.
TMC2330A
PRODUCT SPECIFICATION
REV. 1.1.8 10/31/00
3
Table 1. Data Input/Output Formats—Integer Format
Table 2. Data Input/Output Formats—Fractional Format
Notes:
1. -2
15
denotes two’s complement sign bit.
2. NS denotes negative sign, i.e., ‘1’ negates the number.
3. ±2
0
denotes two’s complement sign or highest magnitude bit – since phase angles are modulo 2
π
and phase accumulator is
modulo 2
32
, this bit may be regarded as +
π
or -
π
.
4. All phase angles are in terms of
π
radians, hence notation “x
π
.”
5. If A
CC
= 00, YPIN(15-0) are “don’t cares.”
6. Formats:
T = Two’s Complement
S = Signed Magnitude
U = Unsigned
Port
RTP
TCXY
Bit #
Format
31
30
29
…
16
15
14
…
0
XRIN
XRIN
XRIN
0
1
1
X
0
1
2
15
NS
–2
15
2
14
2
14
2
14
…
…
…
2
0
2
0
2
0
U
S
T
YPIN
YPIN
YPIN
0
1
1
X
0
1
±2
0
NS
–2
15
2
-1
2
14
2
14
2
-2
2
13
2
13
…
…
2
-15
2
0
2
0
2
-16
2
-17
…
2
-31
(x
π
)T/U
S
T
RXOUT
RXOUT
RXOUT
0
0
1
0
1
X
NS
–2
15
2
15
2
14
2
14
2
14
2
0
2
0
2
0
S
T
U
PYOUT
PYOUT
PYOUT
0
0
1
0
1
X
NS
–2
15
±2
0
2
14
2
14
2
-1
2
0
2
0
2
-15
(x
π
)T/U
S
T
Port
RTP
TCXY
Bit #
Format
31
30
29
…
16
15
14
…
0
XRIN
XRIN
XRIN
0
1
1
X
0
1
2
0
NS
–2
0
2
-1
2
-1
2
-1
…
…
…
2
-15
2
-15
2
-15
U
S
T
YPIN
YPIN
YPIN
0
1
1
X
0
1
±2
0
NS
-2
0
2
-1
2
-1
2
-1
2
-2
2
-2
2
-2
…
…
…
2
-15
2
-15
2
-15
2
-16
2
-17
…
2
-31
(x
π
)T/U
S
T
RXOUT
RXOUT
RXOUT
0
0
1
0
1
X
NS
–2
0
2
0
2
-1
2
-1
2
-1
…
…
…
2
-15
2
-15
2
-15
S
T
U
PYOUT
PYOUT
PYOUT
0
0
1
0
1
X
NS
–2
0
±2
0
2
-1
2
-1
2
-1
…
…
…
2
-15
2
-15
2
-15
(x
π
)T/U
S
T
HEX
U
T
S
FFFF
…
8001
8000
7FFF
…
0001
0000
65535
…
32769
32768
32767
…
1
0
–1
…
-32767
-32768
32767
…
1
0
-32767
…
-1
0
32767
…
1
0
