April 2001
ï›™2003 Fairchild Semiconductor Corporation
Si3455DV Rev A1 (W)
Si3455DV
Single P-Channel Logic Level PowerTrench

MOSFET
General Description
This P-Channel Logic Level MOSFET is produced
using Fairchild’s advanced PowerTrench process. It
has been optimized for battery power management
applications.
Applications
• Battery management
• Load switch
• Battery protection
Features
• –3.6 A, –30 V. R
DS(ON)
= 75 m
Ω @ V
GS
= –10 V
R
DS(ON)
= 125 m
Ω @ V
GS
= –4.5 V
• Low gate charge
• High performance trench technology for extremely
low R
DS(ON)
D
D
D
S
D
G
SuperSOT -6
TM
6
5
4
1
2
3
Absolute Maximum Ratings
T
A
=25
o
C unless otherwise noted
Symbol Parameter
Ratings
Units
V
DSS
Drain-Source Voltage
–30
V
V
GSS
Gate-Source
Voltage
±20
V
I
D
Drain Current – Continuous
(Note 1a)
–3.6 A
–
Pulsed
–10
Maximum Power Dissipation
(Note 1a)
1.6 W
P
D
(Note 1b)
0.8
T
J
, T
STG
Operating and Storage Junction Temperature Range
–55 to +150
°C
Thermal Characteristics
R
θJA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
78
°C/W
R
θJC
Thermal Resistance, Junction-to-Case
(Note 1)
30
°C/W
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
.455 Si3455DV
7’’
8mm 3000
units
Si3455DV
Si3455DV Rev A1 (W)
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Symbol Parameter
Test
Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage
V
GS
= 0 V, I
D
= –250
µA
–30 V
∆BV
DSS
∆T
J
Breakdown Voltage Temperature
Coefficient
I
D
= –250
µA,Referenced to 25°C
–22 mV/
°C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= –24 V, V
GS
= 0 V
–1
µA
I
GSSF
Gate–Body Leakage, Forward
V
GS
= 20 V,
V
DS
= 0 V
100
nA
I
GSSR
Gate–Body Leakage, Reverse
V
GS
= –20 V
V
DS
= 0 V
–100
nA
On Characteristics
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= –250
µA
–1 –1.9 –3 V
∆V
GS(th)
∆T
J
Gate Threshold Voltage
Temperature Coefficient
I
D
= –250
µA,Referenced to 25°C
4
mV/
°C
R
DS(on)
Static Drain–Source
On–Resistance
V
GS
= –10 V,
I
D
= –3.6 A
V
GS
= –4.5 V, I
D
= –2.7 A
V
GS
= –10 V, I
D
= –3.6AT
J
=125
°
63
100
90
75
125
113
m
Ω
I
D(on)
On–State Drain Current
V
GS
= –4.5 V,
V
DS
= –5 V
–5
A
g
FS
Forward
Transconductance V
DS
= –5 V,
I
D
= –3.6 A
6
S
Dynamic Characteristics
C
iss
Input
Capacitance
298
pF
C
oss
Output
Capacitance
83
pF
C
rss
Reverse Transfer Capacitance
V
DS
= –15 V,
V
GS
= 0 V,
f = 1.0 MHz
39 pF
Switching Characteristics
(Note 2)
t
d(on)
Turn–On
Delay
Time
6
12
ns
t
r
Turn–On Rise Time
13
23
ns
t
d(off)
Turn–Off Delay Time
11
20
ns
t
f
Turn–Off
Fall
Time
V
DD
= –15 V,
I
D
= –1 A,
V
GS
= –10 V,
R
GEN
= 6
Ω
6 12 ns
Q
g
Total Gate Charge
3.6
5
nC
Q
gs
Gate–Source
Charge
1
nC
Q
gd
Gate–Drain
Charge
V
DS
= –15 V,
I
D
= –3.6 A,
V
GS
= –.5 V
1.2 nC
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
–1.3
A
V
SD
Drain–Source
Diode
Forward
Voltage
V
GS
= 0 V, I
S
= –1.3 A
(Note 2)
–0.8
–1.2 V
Notes:
1. R
θJA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θJC
is guaranteed by design while R
θCA
is determined by the user's board design.
a) 78°C/W
when
mounted on a 1in
2
pad
of 2 oz copper
b) 156°C/W
when
mounted
on a minimum pad of 2 oz
copper
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300
µs, Duty Cycle < 2.0%
Si3455DV
Si3455DV Rev A1 (W)
Typical Characteristics
0
3
6
9
12
15
0
1
2
3
4
5
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
-I
D
, DRAI
N CURRENT (
A
)
V
GS
= -10V
-3.5V
-3.0V
-4.5V
-4.0V
-5.0V
-6.0V
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0
3
6
9
12
15
-I
D
, DRAIN CURRENT (A)
R
DS(O
N)
, NORMALI
Z
ED
DRAI
N-
SOURCE ON-
R
ESI
STANCE
V
GS
= -3.5V
-6.0V
-5.0V
-4.0V
-10V
-4.5V
-7.0V
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.6
0.8
1
1.2
1.4
1.6
-50
-25
0
25
50
75
100
125
150
T
J
, JUNCTION TEMPERATURE (
o
C)
R
DS
(O
N)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
I
D
= -3.6A
V
GS
= -10V
0.05
0.1
0.15
0.2
0.25
0.3
2
4
6
8
10
-V
GS
, GATE TO SOURCE VOLTAGE (V)
R
DS(O
N)
, ON-
R
ESI
STANCE (
O
HM)
I
D
= -1.8A
T
A
= 125
o
C
T
A
= 25
o
C
Figure 3. On-Resistance Variation
withTemperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
0
2
4
6
8
10
1
2
3
4
5
-V
GS
, GATE TO SOURCE VOLTAGE (V)
-I
D
, DRAI
N CURRENT (
A
)
T
A
= -55
o
C
25
o
C
125
o
C
V
DS
= -5.0V
0.0001
0.001
0.01
0.1
1
10
0
0.2
0.4
0.6
0.8
1
1.2
-V
SD
,
BODY DIODE FORWARD VOLTAGE (V)
-I
S
, REVERSE DRAI
N CURRENT (
A
)
V
GS
= 0V
T
A
= 125
o
C
25
o
C
-55
o
C
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
Si3455DV
Si3455DV Rev A1 (W)
Typical Characteristics
0
2
4
6
8
10
0
1.4
2.8
4.2
5.6
7
Q
g
, GATE CHARGE (nC)
-V
GS
, GATE-
SOURCE VOLTAGE (
V
)
I
D
= -3.6A
V
DS
= -5V
-10V
-15V
0
100
200
300
400
0
6
12
18
24
30
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (
pF)
C
ISS
C
OSS
C
RSS
f = 1 MHz
V
GS
= 0 V
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
0.01
0.1
1
10
100
0.1
1
10
100
-V
DS
, DRAIN-SOURCE VOLTAGE (V)
-I
D
, DRAIN CURRENT (A)
DC
1s
100ms
100
µs
R
DS(ON)
LIMIT
V
GS
= -10V
SINGLE PULSE
R
θJA
= 156
o
C/W
T
A
= 25
o
C
10ms
1ms
10
µs
0
2
4
6
8
10
0.01
0.1
1
10
100
t
1
, TIME (sec)
P(pk), PEAK TRANSIENT POWER (W)
SINGLE PULSE
R
θJA
= 156°C/W
T
A
= 25°C
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum
Power Dissipation.
0.01
0.1
1
0.0001
0.001
0.01
0.1
1
10
100
1000
t
1
, TIME (sec)
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
R
θJA
(t) = r(t) + R
θJA
R
θJA
= 156
o
C/W
T
J
- T
A
= P * R
θJA
(t)
Duty Cycle, D = t
1
/ t
2
P(pk)
t
1
t
2
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
D = 0.5
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
Si3455DV
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILDÂ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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