© 2002 Fairchild Semiconductor Corporation
DS500378
www.fairchildsemi.com
September 2001
Revised July 2002
FSTD32
21
1 4
0
/48-
Bit
Bus
Swit
ch wi
th
Level
Shi
ft
ing
FSTD32211
40/48-Bit Bus Switch with Level Shifting
General Description
The Fairchild Switch FSTD32211 provides up to 48-bits of
high-speed CMOS TTL-compatible bus switching. The low
on resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise. A diode to V
CC
has been
integrated into the circuit to allow for level shifting between
5V inputs and 3.3V outputs.
The device can be organized as four 12-bit, two 24-bit, or
one 48-bit bus switch. When routed as a 40-bit bus switch,
the device can be organized as four 10-bit, two 20-bit or
one 40-bit bus switch. When OE
1
is LOW, the switch is ON
and Port 1A is connected to Port 1B. When OE
2
is LOW,
the switch is ON and Port 2A is connected to Port 2B.
When OE
3
is LOW, the switch is ON and Port 3A is con-
nected to Port 3B. When OE
4
is LOW, the switch is ON and
Port 4A is connected to Port 4B. When OE
1
, OE
2
, OE
3
, or
OE
4
are HIGH, a high impedance state exists between the
A and B Ports.
Features
I
4
Ω
switch connection between two ports
I
Voltage level shifting
I
Minimal propagation delay through the switch
I
Low l
CC
I
Zero bounce in flow-through mode
I
Control inputs compatible with TTL level
I
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Order Number
Package Number
Package Description
FSTD32211G
(Note 1)(Note 2)
BGA114A
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
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2
FSTD3221
1
Connection Diagram
(Top Thru View)
Pin Descriptions
FBGA Pin Assignments
(40-Bit Routing)
Truth Tables
Pin Name
Description
OE
1
, OE
2
, OE
3
, OE
4
Bus Switch Enables
1A, 2A, 3A, 4A
Bus A
1B, 2B, 3B, 4B
Bus B
1
2
3
4
5
6
A
1A
2
1A
1
NC
OE
2
1B
1
1B
2
B
1A
4
1A
3
GND
OE
1
1B
3
1B
4
C
1A
6
1A
5
GND
GND
1B
5
1B
6
D
1A
8
1A
7
GND
GND
1B
7
1B
8
E
1A
10
1A
9
V
CC
V
CC
1B
9
1B
10
F
2A
2
2A
1
V
CC
V
CC
2B
1
2B
2
G
2A
4
2A
3
V
CC
GND
2B
3
2B
4
H
2A
6
2A
5
GND
GND
2B
5
2B
6
J
2A
8
2A
7
2A
9
2B
9
2B
7
2B
8
K
2A
10
3A
10
GND
GND
3B
10
2B
10
L
3A
9
3A
8
GND
GND
3B
8
3B
9
M
3A
7
3A
6
GND
V
CC
3B
6
3B
7
N
3A
5
3A
4
V
CC
V
CC
3B
4
3B
5
P
3A
3
3A
2
V
CC
V
CC
3B
2
3B
3
R
3A
1
4A
10
GND
GND
4B
10
3B
1
T
4A
9
4A
8
GND
GND
4B
8
4B
9
U
4A
7
4A
6
GND
4B
1
4B
6
4B
7
V
4A
5
4A
4
4A
1
OE
4
4B
4
4B
5
W
4A
3
4A
2
OE
3
NC
4B
2
4B
3
Inputs
Inputs/Outputs
OE
1
OE
2
1A, 1B
2A, 2B
L
L
1A
=
1B
2A
=
2B
L
H
1A
=
1B
Z
H
L
Z
2A
=
2B
H
H
Z
Z
Inputs
Inputs/Outputs
OE
3
OE
4
3A, 3B
4A, 4B
L
L
3A
=
3B
4A
=
4B
L
H
3A
=
3B
Z
H
L
Z
4A
=
4B
H
H
Z
Z
3
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FSTD32
21
1
Connection Diagram
(Top Thru View)
Pin Descriptions
FBGA Pin Assignments
(48-Bit Routing)
Truth Tables
Pin Name
Description
OE
1
, OE
2
, OE
3
, OE
4
Bus Switch Enables
1A, 2A, 3A, 4A
Bus A
1B, 2B, 3B, 4B
Bus B
1
2
3
4
5
6
A
1A
2
1A
1
NC
OE
2
1B
1
1B
2
B
1A
4
1A
3
1A
7
OE
1
1B
3
1B
4
C
1A
6
1A
5
GND
1B
7
1B
5
1B
6
D
1A
10
1A
9
1A
8
1B
8
1B
9
1B
10
E
1A
12
1A
11
2A
1
2B
1
1B
11
1B
12
F
2A
4
2A
3
2A
2
2B
2
2B
3
2B
4
G
2A
6
2A
5
V
CC
GND
2B
5
2B
6
H
2A
8
2A
7
GND
GND
2B
7
2B
8
J
2A
10
2A
9
2A
11
2B
11
2B
9
2B
10
K
2A
12
3A
12
GND
GND
3B
12
2B
12
L
3A
11
3A
10
GND
GND
3B
10
3B
11
M
3A
9
3A
8
GND
V
CC
3B
8
3B
9
N
3A
7
3A
6
3A
2
3B
2
3B
6
3B
7
P
3A
5
3A
4
3A
1
3B
1
3B
4
3B
5
R
3A
3
4A
12
4A
8
4B
8
4B
12
3B
3
T
4A
11
4A
10
4A
7
4B
7
4B
10
4B
11
U
4A
9
4A
6
GND
4B
1
4B
6
4B
9
V
4A
5
4A
4
4A
1
OE
4
4B
4
4B
5
W
4A
3
4A
2
OE
3
NC
4B
2
4B
3
Inputs
Inputs/Outputs
OE
1
OE
2
1A, 1B
2A, 2B
L
L
1A
=
1B
2A
=
2B
L
H
1A
=
1B
Z
H
L
Z
2A
=
2B
H
H
Z
Z
Inputs
Inputs/Outputs
OE
3
OE
4
3A, 3B
4A, 4B
L
L
3A
=
3B
4A
=
4B
L
H
3A
=
3B
Z
H
L
Z
4A
=
4B
H
H
Z
Z
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4
FSTD3221
1
Absolute Maximum Ratings
(Note 3)
Recommended Operating
Conditions
(Note 6)
Note 3: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 4: V
S
is the voltage observed/applied at either A or B Ports across the
switch.
Note 5: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 6: Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
Note 7: Typical values are at V
CC
=
5.0V and T
A
=
+
25
°
C
Note 8: Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the
voltages on the two (A or B) pins.
Supply Voltage (V
CC
)
0.5V to
+
7.0V
DC Switch Voltage (V
S
) (Note 4)
−
0.5V to
+
7.0V
DC Input Control Pin Voltage (V
IN
)(Note 5)
−
0.5V to
+
7.0V
DC Input Diode Current (l
IK
) V
IN
<
0V
−
50 mA
DC Output (I
OUT
) 128
mA
DC V
CC
/GND Current (I
CC
/I
GND
)
+
/
−
100 mA
Storage Temperature Range (T
STG
)
−
65
°
C to
+
150
°
C
Power Supply Operating (V
CC)
4.5V to 5.5V
Input Voltage (V
IN
)
0V to 5.5V
Output Voltage (V
OUT
)
0V to 5.5V
Input Rise and Fall Time (t
r
, t
f
)
Switch Control Input
0 ns/V to 5 ns/V
Switch I/O
0 ns/V to DC
Free Air Operating Temperature (T
A
)
-40
°
C to
+
85
°
C
Symbol
Parameter
V
CC
(V)
T
A
=
−
40
°
C to
+
85
°
C
Units
Conditions
Min
Typ
(Note 7)
Max
V
IK
Clamp Diode Voltage
4.5
−
1.2
V
I
IN
=
−
18 mA
V
IH
HIGH Level Input Voltage
4.5 - 5.5
2.0
V
V
IL
LOW Level Input Voltage
4.5 - 5.5
0.8
V
V
OH
HIGH Level
4.5 - 5.5
See Figure 3
V
I
I
Input Leakage Current
5.5
±
1.0
µ
A
0
≤
V
IN
≤
5.5V
0
10
µ
A
V
IN
=
5.5V
I
OZ
OFF-STATE Leakage Current
5.5
±
1.0
µ
A
0
≤
A, B
≤
V
CC
R
ON
Switch On Resistance
4.5
4
7
Ω
V
IN
=
0V, I
IN
=
64 mA
(Note 8)
4.5
4
7
Ω
V
IN
=
0V, I
IN
=
30 mA
4.5
35
50
Ω
V
IN
=
2.4V, I
IN
=
15 mA
I
CC
Quiescent Supply Current
5.5
1.5
mA
OE
1
=
OE
2
=
GND
V
IN
=
V
CC
or GND, I
OUT
=
0
10
µ
A
OE
1
=
OE
2
=
V
CC
V
IN
=
V
CC
or GND, I
OUT
=
0
∆
I
CC
Increase in I
CC
per Input
5.5
2.5
mA
One Input at 3.4V
Other Inputs at V
CC
or GND
5
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FSTD32
21
1
AC Electrical Characteristics
Note 9: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
(Note 10)
Note 10: T
A
=
+
25
°
C, f
=
1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50
Ω
source terminated in 50
Ω
Note: C
L
includes load and stray capacitance
Note: Input PRR
=
1.0 MHz, t
W
=
500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
Symbol
Parameter
T
A
=
−
40
°
C to
+
85
°
C,
Units
Conditions
Figure
Number
C
L
=
50pF, RU
=
RD
=
500
Ω
V
CC
=
4.5 – 5.5V
Min
Max
t
PHL
, t
PLH
Propagation Delay Bus to Bus (Note 9)
0.25
ns
V
I
=
OPEN
Figures
1, 2
t
PZH
, t
PZL
Output Enable Time
1.5
10.0
ns
V
I
=
7V for t
PZL
Figures
1, 2
V
I
=
OPEN for t
PZH
t
PHZ
, t
PLZ
Output Disable Time
1.5
9.0
ns
V
I
=
7V for t
PLZ
Figures
1, 2
V
I
=
OPEN for t
PHZ
Symbol
Parameter
Typ
Max
Units
Conditions
C
IN
Control Pin Input Capacitance
3
pF
V
CC
=
5.0V
C
I/O
Input/Output Capacitance
6
pF
V
CC
, OE
=
5.0V
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6
FSTD3221
1
Output Voltage HIGH vs. Supply Voltage
FIGURE 3.
7
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FSTD32
21
1 4
0
/48-
Bit
Bus
Swit
ch wi
th
Level
Shi
ft
ing
Physical Dimensions
inches (millimeters) unless otherwise noted
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA114A
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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