background image
May 2001
QFET
TM
FQL40N50
©2001 Fairchild Semiconductor Corporation
Rev. A1. May 2001
FQL40N50
500V N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supply, power
factor correction, motor drive and welding machine.
Features
• 40A, 500V, R
DS(on)
= 0.11
Ω
@V
GS
= 10 V
• Low gate charge ( typical 155 nC)
• Low Crss ( typical 95 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
Absolute Maximum Ratings
T
C
= 25°C unless otherwise noted
Thermal Characteristics
Symbol
Parameter
FQL40N50
Units
V
DSS
Drain-Source Voltage
500
V
I
D
Drain Current
- Continuous (T
C
= 25°C)
40
A
- Continuous (T
C
= 100°C)
25
A
I
DM
Drain Current
- Pulsed
(Note 1)
160
A
V
GSS
Gate-Source Voltage
±
30
V
E
AS
Single Pulsed Avalanche Energy
(Note 2)
1780
mJ
I
AR
Avalanche Current
(Note 1)
40
A
E
AR
Repetitive Avalanche Energy
(Note 1)
46
mJ
dv/dt
Peak Diode Recovery dv/dt
(Note 3)
4.5
V/ns
P
D
Power Dissipation (T
C
= 25°C)
460
W
- Derate above 25°C
3.7
W/°C
T
J
, T
STG
Operating and Storage Temperature Range
-55 to +150
°C
T
L
Maximum lead temperature for soldering purposes,
1/8
"
from case for 5 seconds
300
°C
Symbol
Parameter
Typ
Max
Units
R
θ
JC
Thermal Resistance, Junction-to-Case
--
0.27
°C
/
W
R
θ
CS
Thermal Resistance, Case-to-Sink
0.1
--
°C
/
W
R
θ
JA
Thermal Resistance, Junction-to-Ambient
--
30
°C
/
W
! "
!
!
!
"
"
"
! "
!
!
!
"
"
"
S
D
G
TO-264
FQL Series
G
S
D
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FQL40N50
Rev. A1. May 2001
©2001 Fairchild Semiconductor Corporation
Electrical Characteristics
T
C
= 25°C unless otherwise noted
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 2.0mH, I
AS
= 40A, V
DD
= 50V, R
G
= 25
Ω,
Starting T
J
= 25°C
3. I
SD
≤
40A, di/dt
≤
200A/
µ
s, V
DD
≤
BV
DSS,
Starting T
J
= 25°C
4. Pulse Test : Pulse width
≤
300
µ
s, Duty cycle
≤
2%
5. Essentially independent of operating temperature
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250
µ
A
500
--
--
V
∆
BV
DSS
/
∆
T
J
Breakdown Voltage Temperature
Coefficient
I
D
= 250
µ
A, Referenced to 25°C
--
0.48
--
V/°C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 500 V, V
GS
= 0 V
--
--
1
µ
A
V
DS
= 400 V, T
C
= 125°C
--
--
10
µ
A
I
GSSF
Gate-Body Leakage Current, Forward
V
GS
= 30 V, V
DS
= 0 V
--
--
100
nA
I
GSSR
Gate-Body Leakage Current, Reverse
V
GS
= -30 V, V
DS
= 0 V
--
--
-100
nA
On Characteristics
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250
µ
A
3.0
--
5.0
V
R
DS(on)
Static Drain-Source
On-Resistance
V
GS
= 10 V, I
D
= 20 A
--
0.085
0.11
Ω
g
FS
Forward Transconductance
V
DS
= 50 V, I
D
= 20 A
--
29
--
S
Dynamic Characteristics
C
iss
Input Capacitance
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
--
5800
7500
pF
C
oss
Output Capacitance
--
880
1150
pF
C
rss
Reverse Transfer Capacitance
--
95
120
pF
Switching Characteristics
t
d(on)
Turn-On Delay Time
V
DD
= 250 V, I
D
= 40 A,
R
G
= 25
Ω
--
140
290
ns
t
r
Turn-On Rise Time
--
440
890
ns
t
d(off)
Turn-Off Delay Time
--
350
700
ns
t
f
Turn-Off Fall Time
--
250
500
ns
Q
g
Total Gate Charge
V
DS
= 400 V, I
D
= 40 A,
V
GS
= 10 V
--
155
200
nC
Q
gs
Gate-Source Charge
--
37
--
nC
Q
gd
Gate-Drain Charge
--
78
--
nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain-Source Diode Forward Current
--
--
40
A
I
SM
Maximum Pulsed Drain-Source Diode Forward Current
--
--
160
A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 40 A
--
--
1.4
V
t
rr
Reverse Recovery Time
V
GS
= 0 V, I
S
= 40 A,
dI
F
/ dt = 100 A/
µ
s
--
520
--
ns
Q
rr
Reverse Recovery Charge
--
8.0
--
µ
C
(Note 4)
(Note 4, 5)
(Note 4, 5)
(Note 4)
background image
FQL40N50
©2001 Fairchild Semiconductor Corporation
Rev. A1. May 2001
0
30
60
90
120
150
180
0
2
4
6
8
10
12
V
DS
= 250V
V
DS
= 100V
V
DS
= 400V
※
Note : I
D
= 40 A
V
GS
, G
at
e-
S
our
ce
V
ol
tag
e [
V
]
Q
G
, Total Gate Charge [nC]
10
-1
10
0
10
1
0
2000
4000
6000
8000
10000
12000
C
iss
= C
gs
+ C
gd
(C
ds
= shorted)
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
※
Notes :
1. V
GS
= 0 V
2. f = 1 MHz
C
rss
C
oss
C
iss
C
apa
ci
ta
nc
e [
pF
]
V
DS
, Drain-Source Voltage [V]
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
10
-1
10
0
10
1
10
2
25
℃
150
℃
※
Notes :
1. V
GS
= 0 V
2. 250
μ
s Pulse Test
I
DR
, R
ev
er
se D
rai
n C
ur
re
nt
[
A]
V
SD
, Source-Drain Voltage [V]
0
30
60
90
120
150
180
0.1
0.2
0.3
0.4
※
Note : T
J
= 25
℃
V
GS
= 20V
V
GS
= 10V
R
D
S
(on)
[
Ω
],
D
rai
n-
S
ou
rce
O
n-
R
esi
st
ance
I
D
, Drain Current [A]
2
4
6
8
10
10
-1
10
0
10
1
10
2
※
Notes :
1. V
DS
= 50V
2. 250
μ
s Pulse Test
-55
℃
150
℃
25
℃
I
D
, D
ra
in
C
ur
re
nt [A
]
V
GS
, Gate-Source Voltage [V]
10
-1
10
0
10
1
10
0
10
1
10
2
※
Notes :
1. 250
μ
s Pulse Test
2. T
C
= 25
℃
V
GS
Top : 15 V
10 V
8.0 V
7.0 V
6.5 V
6.0 V
Bottom : 5.5 V
I
D
, D
rai
n C
ur
rent
[
A]
V
DS
, Drain-Source Voltage [V]
Typical Characteristics
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
Figure 2. Transfer Characteristics
Figure 1. On-Region Characteristics
background image
FQL40N50
©2001 Fairchild Semiconductor Corporation
Rev. A1. May 2001
1 0
-5
1 0
-4
1 0
-3
1 0
-2
1 0
-1
1 0
0
1 0
1
1 0
-2
1 0
-1
※
N o te s :
1 . Z
θ
J C
( t) = 0 .2 7
℃
/W M a x .
2 . D u ty F a c to r , D = t
1
/t
2
3 . T
J M
- T
C
= P
D M
* Z
θ
J C
( t)
s in g le p u ls e
D = 0 .5
0 .0 2
0 .2
0 .0 5
0 .1
0 .0 1
Z
θ
JC
(t
),
T
h
er
m
a
l R
e
s
p
onse
t
1
, S q u a r e W a v e P u ls e D u r a t io n [ s e c ]
25
50
75
100
125
150
0
10
20
30
40
I
D
, D
rai
n
C
ur
re
nt
[A
]
T
C
, Case Temperature [
℃
]
10
0
10
1
10
2
10
3
10
-1
10
0
10
1
10
2
10
3
10
µ
s
DC
10 ms
1 ms
100
µ
s
Operation in This Area
is Limited by R
DS(on)
※
Notes :
1. T
C
= 25
o
C
2. T
J
= 150
o
C
3. Single Pulse
I
D
, D
rai
n C
ur
re
nt
[A
]
V
DS
, Drain-Source Voltage [V]
-100
-50
0
50
100
150
200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
※
Notes :
1. V
GS
= 10 V
2. I
D
= 20 A
R
DS
(O
N
)
, (
N
or
m
al
iz
ed)
D
rai
n-
Sour
ce O
n-
R
esi
st
ance
T
J
, Junction Temperature [
o
C]
-100
-50
0
50
100
150
200
0.8
0.9
1.0
1.1
1.2
※
Notes :
1. V
GS
= 0 V
2. I
D
= 250
μ
A
BV
DS
S
, (
N
or
m
aliz
ed
)
D
ra
in-
So
ur
ce
B
rea
kd
ow
n V
ol
tag
e
T
J
, Junction Temperature [
o
C]
Typical Characteristics
(Continued)
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case Temperature
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
Figure 11. Transient Thermal Response Curve
t
1
P
DM
t
2
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FQL40N50
©2001 Fairchild Semiconductor Corporation
Rev. A1. May 2001
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
Unclamped Inductive Switching Test Circuit & Waveforms
Charge
V
GS
10V
Q
g
Q
gs
Q
gd
3mA
V
GS
DUT
V
DS
300nF
50K
Ω
200nF
12V
Same Type
as DUT
Charge
V
GS
10V
Q
g
Q
gs
Q
gd
3mA
V
GS
DUT
V
DS
300nF
50K
Ω
200nF
12V
Same Type
as DUT
V
GS
V
DS
10%
90%
t
d(on)
t
r
t
on
t
off
t
d(off)
t
f
V
DD
10V
V
DS
R
L
DUT
R
G
V
GS
V
GS
V
DS
10%
90%
t
d(on)
t
r
t
on
t
off
t
d(off)
t
f
V
DD
10V
V
DS
R
L
DUT
R
G
V
GS
E
AS
=
L I
AS
2
----
2
1
--------------------
BV
DSS
- V
DD
BV
DSS
V
DD
V
DS
BV
DSS
t
p
V
DD
I
AS
V
DS
(t)
I
D
(t)
Time
10V
DUT
R
G
L
I
D
t
p
E
AS
=
L I
AS
2
----
2
1
E
AS
=
L I
AS
2
----
2
1
----
2
1
--------------------
BV
DSS
- V
DD
BV
DSS
V
DD
V
DS
BV
DSS
t
p
V
DD
I
AS
V
DS
(t)
I