©
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 1
1
Publication Order Number:
MC14001B/D
MC14001B Series
B-Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
•
All Outputs Buffered
•
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
•
Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
•
Pin–for–Pin Replacements for Corresponding CD4000 Series B
Suffix Devices
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 1.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
– 0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
– 0.5 to V
DD
+ 0.5
V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
±
10
mA
P
D
Power Dissipation,
per Package (Note 2.)
500
mW
T
A
Ambient Temperature Range
– 55 to +125
°
C
T
stg
Storage Temperature Range
– 65 to +150
°
C
T
L
Lead Temperature
(8–Second Soldering)
260
°
C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
Device
Description
DEVICE INFORMATION
MC14001B
Quad 2–Input NOR Gate
MC14011B
Quad 2–Input NAND Gate
MC14023B
Triple 3–Input NAND Gate
MC14025B
Triple 3–Input NOR Gate
MC14071B
Quad 2–Input OR Gate
MARKING
DIAGRAMS
1
14
PDIP–14
P SUFFIX
CASE 646
MC140XXBCP
AWLYYWW
SOIC–14
D SUFFIX
CASE 751A
TSSOP–14
DT SUFFIX
CASE 948G
1
14
140XXB
AWLYWW
14
0XXB
ALYW
1
14
XX
= Specific Device Code
A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
SOEIAJ–14
F SUFFIX
CASE 965
1
14
MC140XXB
AWLYWW
MC14073B
Triple 3–Input AND Gate
MC14081B
Quad 2–Input AND Gate
MC14082B
Dual 4–Input AND Gate
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
