REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADM1051/ADM1051A
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
Precision Dual Voltage
Regulator Controllers
FUNCTIONAL BLOCK DIAGRAM
SHDN1
V
CC
50 A
BANDGAP
REFERENCE
HICCUP
COMPARATOR
100 F
2 100 F
V
OUT1
CONTROL
AMPLIFIER
FORCE 1
SENSE 1
ADM1051/ADM1051A
SHDN2
HICCUP
COMPARATOR
GND
V
CC
V
IN
3.3V
CONTROL
AMPLIFIER
FORCE 2
SENSE 2
V
CC
SHUTDOWN
CONTROL
100 F
2 100 F
V
OUT2
V
IN
3.3V
SHUTDOWN
CONTROL
V
CC
50 A
CLK/DELAY
GENERATOR
POWER-ON
RESET
CLOCK
OSCILLATOR
NO CONNECTION
ON ADM1051A
FEATURES
Two Independent Controllers on One Chip
1.515 V and 1.818 V Outputs
Shutdown Inputs to Control Each Channel
Compatible with PC Motherboard TYPEDET Signal
2.5% Accuracy Over, Line, Load, and Temperature
Low Quiescent Current
Low Shutdown Current
Works with External N-Channel MOSFETs for Low Cost
“Hiccup Mode” Fault Protection
No External Voltage or Current Setting Resistors
1.8 V/3.3 V ICH Sequenced Power-Up on ADM1051A
Small, 8-Lead SOIC Package
APPLICATIONS
Desktop Computers
Servers
Workstations
GENERAL DESCRIPTION
The ADM1051/ADM1051A are dual, precision, voltage regula-
tor controllers intended for power rail generation and active bus
termination on personal computer motherboards. They contain a
precision 1.2 V bandgap reference and two channels consisting of
control amplifiers driving external power devices. Each channel
has a shutdown input to turn off amplifier output and Hiccup
Mode protection circuitry for the external power device. The
shutdown input on the 1.5 V channel can also be used with the
TYPEDET signal on a PC motherboard to select the output voltage.
The ADM1051/ADM1051A operate from a 12 V supply, which
gives sufficient headroom for the amplifiers to drive external
N-channel MOSFETs, operating as source-followers, as the
external series pass devices. This has the advantage that N-
channel devices are cheaper than P-channel devices of similar
performance, and the circuit is easier to stabilize than one using
P-channel devices in a common-source configuration.
REV. 0
–2–
ADM1051/ADM1051A–SPECIFICATIONS
(V
CC
= 12 V 6%, V
IN
= 3.3 V, T
A
= 0 C to 70 C, both
channels, unless otherwise noted. See Test Circuit.)
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
OUTPUT VOLTAGE
Channel 1
1.515
V
SHDN1 Floating
Channel 2
1.818
V
OUTPUT VOLTAGE ACCURACY
–2.5
+2.5
%
V
IN
= 3.0 V to 3.6 V, I
OUT
= 10 mA to 1 A
Load Regulation
–5
+5
mV
V
IN
= 3.3 V, I
OUT
= 10 mA to 1 A
1
Line Regulation
–5
+5
mV
V
IN
= 3.0 V to 3.6 V, I
OUT
= 1 A
1
5 VSB Supply Voltage Required for
4.6
V
Test Circuit as Figure 7.
2
I
LOAD
= 500 mA
Channel 2 Regulation
CONTROL AMPLIFIER
Control Amplifier Open-Loop Gain
100
dB
Control Amplifier Slew Rate
3
V/
µs
Closed-Loop Settling Time
5
µs
I
O
= 10 mA to 2 A
Turn-On Time
5
µs
To 90% of Force High Output Level (C
L
= 470 pF)
Sense Input Impedance
1
50
k
Ω
Force Output Voltage Swing, V
F
(High)
10
V
R
L
= 10 k
Ω to GND
Force Output Voltage Swing, V
F
(Low)
2
V
R
L
= 10 k
Ω to V
CC
HICCUP MODE
Hiccup Mode Hold-Off Time
30
60
90
ms
See Figure 4
Hiccup Mode Threshold
0.8
× V
OUT
V
Hiccup Comparator Glitch Immunity
100
µs
Hiccup Mode On-Time
0.5
1.0
1.5
ms
Hiccup Mode Off-Time
20
40
60
ms
Power-On Reset Threshold
6
9
V
SHUTDOWN,
SHDN1
Mode 1 (Shutdown)
0.8
V
Mode 2 (1.5 V Out)
2
3.9
V
Mode 3 (3.3 V Out)
4.3
5.3
V
Mode 4 (1.5 V Out)
6.2
12
V
SHUTDOWN,
SHDN2
Shutdown Input Low Voltage, V
IL
0.8
V
Shutdown Input High Voltage, V
IH
2.0
V
Supply Current, Normal Operation
2.4
4.0
mA
Shutdown Inputs Floating
Supply Current, Shutdown Mode
600
1000
µA
Both Channels Shut Down
NOTES
1
Guaranteed by design.
2
5 VSB Supply is connected to, and measured at anode of Schottky Diode.
Specifications subject to change without notice.
REV. 0
ADM1051/ADM1051A
–3–
ABSOLUTE MAXIMUM RATINGS
*
(T
A
= 25
°C unless otherwise noted)
V
CC
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V
SHDN1, SHDN2 to GND . . . . . . . . –0.3 V to (V
CC
+ 0.3 V)
SENSE 1, SENSE 2 to GND . . . . . . . . . . . –0.3 V to +5.5 V
FORCE 1, FORCE 2 . . . . . . . Short-Circuit to GND or V
CC
Continuous Power Dissipation (T
A
= 70
°C) . . . . . . . 650 mW
8-Lead SOIC (Derate 8.3 mW/
°C Above 70°C)
Operating Temperature Range
Commercial (J Version) . . . . . . . . . . . . . . . . . . 0
°C to 70°C
Storage Temperature Range . . . . . . . . . . . –65
°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300
°C
*This is a stress rating only; functional operation of the device at these or any other
conditions above those indicated in the operation sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended
periods of time may affect reliability.
THERMAL CHARACTERISTICS
8-Lead Small Outline Package:
θ
JA
= 150
°C/W
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
ADM1051JR
0
°C to 70°C
8-Lead SOIC
R-8
ADM1051AJR
0
°C to 70°C
8-Lead SOIC
R-8
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1
FORCE 2
Output of Channel 2 control amplifier
to gate of external N-channel MOSFET.
2
SENSE 2
Input from source of external MOSFET
to inverting input of Channel 2 control
amplifier, via output voltage-setting
feedback resistor network.
3
SHDN2
Digital Input. Active-low shutdown
control with 50
µA internal pull-up. The
output of Channel 2 control amplifier goes
to ground when
SHDN2 is taken low.
4
GND
Device Ground Pin.
5
SHDN1
Digital Input. Active-low shutdown con-
trol with 50
µA internal pull-up. See text for
more details of
SHDN1 functionality.
6
SENSE 1
Input from source of external MOSFET to
inverting input of Channel 1 control ampli-
fier, via output voltage-setting feedback
resistor network.
7
FORCE 1
Output of Channel 1 control amplifier to
gate of external N-channel MOSFET.
8
V
CC
12 V Supply.
SHDN1
V
CC
ADM1051/
ADM1051A
SHDN2
1 F
LEAVE OPEN OR
CONNECT TO
LOGIC SIGNALS
IF SHUTDOWN
REQUIRED
PHD55N03LT
FORCE 2
SENSE 2
100 F
2 100 F
V
OUT1
FORCE 1
SENSE 1
V
IN
3.3V
12V
MTD3055VL
100 F
2 100 F
V
OUT2
V
IN
3.3V
Figure 1. Test Circuit
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
FORCE 2
SENSE 2
SHDN2
V
CC
FORCE 1
SENSE 1
SHDN1
GND
ADM1051/
ADM1051A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM1051/ADM1051A features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
ADM1051/ADM1051A
–4–
–Typical Performance Characteristics
2
1
Ch
1
500mV
Ch2
500mV
M
1.00 s
Ch1
3.46
V
Ch4
500mV
Tek
S
TOP
:
Single
Seq
50.0MS/
S
TPC 1. Line Transient Response, Channel 1 and
Channel 2
85 C
V
IN
– V
1.500
3.0
V
OUT
– V
3.1
3.2
3.3
3.4
3.5
3.6
1.502
1.504
1.506
1.508
1.510
1.512
1.514
25 C
TPC 2. Line Regulation, Channel 1
V
IN
– V
1.8155
3.0
V
OUT
–
V
3.1
3.2
3.3
3.4
3.5
3.6
1.8160
1.8165
1.8175
1.8185
1.8190
1.8200
1.8205
1.8170
1.8180
1.8195
85 C
25 C
TPC 3. Line Regulation, Channel 2
CURRENT – A
1.50
OUTPUT
–
V
0
1
1.51
1.52
1.53
1.55
1.54
TPC 4. Load Regulation, Channel 1
CURRENT – A
1.795
OUTPUT
–
V
0
1
1.800
1.805
1.810
1.825
1.815
1.820
TPC 5. Load Regulation, Channel 2
FREQUENCY – Hz
–70
RIPPLE REJECTION
–
dB
–60
–40
–30
10
–20
0
–50
100
10
10k
100k
10M
1k
1M
–10
CHANNEL 1
CHANNEL 2
IL = 10mA
TPC 6. V
CC
Supply Ripple Rejection
REV. 0
–5–
ADM1051/ADM1051A
TEMPERATURE – C
1.40
OUTPUT
–
V
0
85
1.45
1.50
1.55
1.85
1.70
1.80
1.60
1.65
1.75
25
1.8V
CHANNEL
1.5V
CHANNEL
TPC 7. Regulator Output Voltage vs. Temperature
BW
20.0mV
M
1.00 s Ch2
–13.6
mV
Tek
S
TOP
:
Single
Seq
50.0ms/
S
TPC 8. Transient Response Channel 1, 10 mA to 2 A
Output Load Step
BW
Ch2
20.0mV
M
1.00 s Ch2
14.8
mV
Tek
Single
Seq
50.0ms/
S
TPC 9. Transient Response Channel 1, 2 A to 10 mA
Output Load Step
BW
Ch2
20.0mV
M
1.00 s Ch2
–16.8
mV
Tek
Single
Seq
50.0ms/
S
TPC 10. Transient Response Channel 2, 10 mA to 2 A
Output Load Step
BW
Ch2
20.0mV
M
1.00 s Ch2
10.4
mV
Tek
Single
Seq
50.0ms/
S
TPC 11. Transient Response Channel 2, 2 A to 10 mA
Output Load Step
Tek
10.0kS/
S
4
Acqs
Ch1
10.0 V
M
5.00ms Ch1
1.0
V
TPC 12. Force Output in Hiccup Mode, Channel 1
REV. 0
ADM1051/ADM1051A
–6–
GENERAL DESCRIPTION
The ADM1051/ADM1051A are dual, precision, voltage regulator
controllers intended for power rail generation and active bus ter-
mination in AGP and ICH applications on personal computer
motherboards. They contain a precision 1.2 V bandgap ref-
erence and two almost identical channels consisting of control
amplifiers driving external power devices. The main difference
between the two channels is the regulated output voltage, defined
by the resistor ratios on the voltage sense inputs of each channel.
Channel 1 has an output of nominally 1.515 V, but can be
switched to a 3.3 V output, while Channel 2 has a nominal
output of 1.818 V. Channel 1 is also optimized for driving
MOSFETs with lower on-resistance and higher gate capaci-
tance, as explained later.
Each channel has a shutdown input to turn off amplifier output
and protection circuitry for the external power device. The
shutdown input of Channel 1 has additional functionality as
described later.
The ADM1051A has some minor differences from the ADM1051
to support power-supply sequencing and voltage requirements
of some I/O control hub chipsets, which dictate that the 1.818 V
rail must never be more than 2 V below the 3.3 V rail.
The ADM1051/ADM1051A operates from a 12 V V
CC
supply.
The outputs are disabled until V
CC
climbs above the Power-On
Reset threshold (6 V–9 V). POR does not apply to Channel 2 of
the ADM1051A. This output will begin to rise as soon as there
is sufficient gate drive to turn on the external MOSFET.
The outputs from the ADM1051/ADM1051A are used to drive
external N-channel MOSFETs, operating as source-followers.
This has the advantage that N-channel devices are cheaper than
P-channel devices of similar performance, and the circuit is easier
to stabilize than one using P-channel devices in a common-
source configuration.
The external power devices are protected by a “Hiccup Mode”
circuit that operates if the circuit goes out of regulation due to
an output short-circuit. In this case the power device is pulsed
on/off with a 1:40 duty-cycle to limit the power dissipation until
the fault condition is removed. Again, to prevent Channel 2
falling more than 2 V below Channel 1, Hiccup Mode does not
operate on Channel 2 of the ADM1051A.
CIRCUIT DESCRIPTION
CONTROL AMPLIFIERS
The reference voltage is amplified and buffered by the control
amplifiers and external MOSFETs, the output voltage of each
channel being determined by the feedback resistor network
between the sense input and the inverting input of the control
amplifier.
The two control amplifiers in the ADM1051/ADM1051A are
almost identical, apart, from the ratios of the feedback resistor
networks on the sense inputs. A power-on reset circuit disables
the amplifier output until V
CC
has risen above the reset thresh-
old (not Channel 2 of ADM1051A).
Each amplifier output drives the gate of an N-channel power
MOSFET, whose drain is connected to the unregulated supply
input and whose source is the regulated output voltage, which is
also fed back to the appropriate sense input of the ADM1051/
ADM1051A. The control amplifiers have high current-drive
capability so they can quickly charge and discharge the gate
capacitance of the external MOSFET, thus giving good transient
response to changes in load or input voltage. In particular,
Channel 1 is optimized to drive MOSFETs with very low on
resistance and correspondingly higher gate capacitance such as
the PHD55N03LT from Philips. This is to minimize voltage
drop across the MOSFET when Channel 1 is used in 3.3 V
mode, as explained later.
SHUTDOWN INPUTS AND TYPEDET COMPATIBILITY
Each channel has a separate shutdown input, which may be
controlled by a logic signal, and allows the output of the regula-
tor to be turned on or off. If the shutdown input is held high or
not connected, the regulator operates normally. If the shutdown
input is held low, the enable input of the control amplifier is turned
off and the amplifier output goes low, turning off the regulator.
The
SHDN1 input on Channel 1 has additional functionality that
can be controlled by the TYPEDET signal on PC motherboards.
The AGP bus on a PC motherboard can have two different modes
of operation, requiring different regulated voltages of 3.3 V or
1.5 V. These two modes are signaled by the TYPEDET signal on
the PC motherboard, as follows:
TYPEDET = 0 V – Regulated Voltage 1.5 V (4
× AGP Graphics)
TYPEDET Floating – Regulated Voltage 3.3 V (2
× AGP Graphics)
5VSB – V
1.855
1.555
3.7
3.9
CHANNEL 2O/P
–
V
4.1
4.7
1.805
1.755
1.655
1.455
1.605
5.3
1.505
1.705
1.405
1.355
1.305
4.3
4.5
4.9
5.1
25 C
VCH2 V's 5VSB ILOAD 500m
70 C
0 C
TPC 13. ADM1051A Channel 2 Output Voltage vs. 5 VSB
Voltage. Test Circuit as Figure 7, I
LOAD
= 500 mA
5VSB – V
1.855
1.555
3.7
3.9
CHANNEL 2O/P
–
V
4.1
4.7
1.805
1.755
1.655
1.455
1.605
5.3
1.505
1.705
1.405
1.355
1.305
4.3
4.5
4.9
5.1
25 C
0 C
70 C
VCH2 V's 5VSB ILOAD 1
TPC 14. ADM1051A Channel 2 Output Voltage vs. 5 VSB
Voltage. Test Circuit as Figure 7, I
LOAD
= 1 A
REV. 0
ADM1051/ADM1051A
–7–
For compatibility with the TYPEDET signal, the regulator output
voltage of Channel 1 may be selected using the Shutdown pin.
This is a multilevel, dual-function input that allows selection of
the regulator output voltage as well as shutdown of the regulator.
By setting
SHDN1 to different voltages, the regulator can be put
into four different operating modes.
Table I. Shutdown Functionality for 1.5 V Channel
SHDN1 Voltage
Mode
Function
< 0.8 V
1
Force Output Low, Regulator
Shutdown
2 V–3.9 V
2
1.5 V Output
4.3 V–5.3 V
3
Force Output High, V
OUT
= 3.3 V
>6.2 V or Floating
4
1.5 V Output
If the
SHDN1 pin is connected to a voltage less than 0.8 V, the
FORCE output will go low and the regulator will be shut down.
If the
SHDN1 pin is connected to a voltage greater than 6.2 V,
or simply left open-circuit, the regulator will operate normally
and provide 1.5 V out. This allows the regulator to operate
normally with no external connection to
SHDN1.
If the
SHDN1 pin is connected to a voltage between 2 V and 3.9 V,
the regulator will also operate normally and provide 1.5 V out.
If the
SHDN1 pin is connected to a voltage between 4.3 V and
5.3 V, the FORCE output will be high and the external MOSFET
will be turned hard on, making the output voltage equal to the 3.3 V
input (less any small drop due to the on-resistance of the MOSFET).
In this mode it is not actually regulating, but simply acting as a
switch for the 3.3 V supply. The voltage drop across the Channel 1
MOSFET in Mode 3 can be minimized by using a MOSFET
with very low on resistance, for which Channel 1 is optimized,
such as the PHD55N03LT.
The latter two modes allow the regulator to be controlled by the
TYPEDET signal simply by using potential divider, as shown in
Figure 2.
TYPEDET
SHDN1
PC 5V SUPPLY
3k
3k
Figure 2. Using
SHDN1 with TYPEDET Signal
A shutdown function can be added by connecting an open-drain/
open-collector logic output to
SHDN1, or by using a totem-pole
logic output with a Schottky diode, as shown in Figure 3.
ADM1051/
ADM1051A
OPEN-DRAIN OR
OPEN-COLLECTOR
OUTPUT
TYPEDET
SHDN1
PC 5V SUPPLY
3k
3k
EN
TYPEDET
ADM1051/
ADM1051A
SHDN1
PC 5V SUPPLY
3k
3k
SCHOTTKY
DIODE
COMPLEMENTARY
OR TOTEM-POLE
OUTPUT
EN
Figure 3. TYPEDET Voltage Selection Combined with
Shutdown Function
When the logic output is high or turned off, the regulator mode
will be controlled by TYPEDET. When the logic output is low,
the regulator will be shut down.
Table II. TYPEDET and Shutdown Truth Table
TYPEDET
EN
Regulator Mode
X
0
Shutdown
0
1
1.5 V
1
1
3.3 V
X = Don’t care.
Note that when Channel 1 of the ADM1051 is set to 3.3 V,
Channel 2 should not be shut down while Channel 1 is active.
12V SUPPLY
V
REF
TURN-ON
THRESHOLD
POR THRESHOLD
4V – 7V
GATE DRIVE TO
EXTERNAL
MOSFET
MOSFET GATE
THRESHOLD
3.3V SUPPLY
TO EXTERNAL
MOSFET DRAIN
CHANNEL 1
OR CHANNEL 2
OUTPUT VOLTAGE
NORMAL
OUTPUT VOLTAGE
FAULT
REMOVED
OUTPUT < 0.8 V
REG
CHANNEL 1
OR CHANNEL 2
OUTPUT CURRENT
HICCUP MODE
HOLD-OFF TIME
2 AMPS
DEVICE ENTERS HICCUP MODE
FAULT CURRENT
1:40 DUTY CYCLE
OFF
ON
Figure 4. Power-On Reset and Hiccup Mode
REV. 0
ADM1051/ADM1051A
–8–
HICCUP MODE FAULT PROTECTION
Hiccup Mode Fault Protection is a simple method of protecting
the external power device without the added cost of external sense
resistors or a current sense pin on the ADM1051/ADM1051A. In
the event of a short-circuit condition at the output, the output
voltage will fall. When the output voltage of a channel falls
20% below the nominal voltage, this is sensed by the hiccup com-
parator and the channel will go into Hiccup Mode, where the
enable signal to the control amplifier is pulsed on and off
with a 1:40 duty cycle. As mentioned earlier, Hiccup Mode
does not operate on Channel 2 of the ADM1051A.
To prevent the device inadvertently going into Hiccup Mode dur-
ing power-up or during channel enabling, the Hiccup Mode is
held off for approximately 60 ms on both channels. By this time
the output voltage should have reached its correct value. In the
case of power-up, the hold-off period starts when V
CC
reaches
the power-on reset threshold of 6 V–9 V. In the case of channel
enabling, the hold-off period starts when
SHDN is taken high.
Note that the hold-off timeout applies to both channels even if
only one channel is disabled/enabled.
As the 3.3 V input to the drain of the MOSFET is not monitored,
it should ideally rise at the same or a faster rate than V
CC
. At the
very least it must be available in time for V
OUT
to reach its final
value before the end of the power-on delay. If the output voltage
is still less than 80% of the correct value after the power-on delay,
the device will go into Hiccup Mode until the output voltage
exceeds 80% of the correct value during a Hiccup Mode on-
period. Of course, if there is a fault condition at the output
during power-up, the device will go into Hiccup Mode after the
power-up delay and remain there until the fault condition is
removed.
The effect of power-on delay is illustrated in Figure 4. This shows
an ADM1051/ADM1051A being powered up with a fault
condition. The output current rises to a very high value dur-
ing the power-on delay, then the device goes into Hiccup Mode
and the output is pulsed on and off at 1:40 duty cycle. When the
fault condition is removed, the output voltage recovers to its
normal value at the end of the Hiccup Mode off period.
The load current at which the ADM1051/ADM1051A will go
into Hiccup Mode is determined by three factors:
• the input voltage to the drain of the MOSFET, V
IN
• the output voltage V
OUT
(–20%)
• the on-resistance of the MOSFET, R
ON
I
HICCUP
= (V
IN<