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1
LTC1065
DC Accurate, Clock-Tunable
Linear Phase 5th Order Bessel
Lowpass Filter
3.4kHz Single 5V Supply Bessel Lowpass Filter
U
A
O
PPLICATI
TYPICAL
D
U
ESCRIPTIO
S
FEATURE
s
Clock-Tunable Cutoff Frequency
s
1mV DC Offset (Typical)
s
80dB CMR (Typical)
s
Internal or External Clock
s
50
µ
V
RMS
Clock Feedthrough
s
100:1 Clock-to-Cutoff Frequency Ratio
s
80
µ
V
RMS
Total Wideband Noise
s
0.004% Noise + THD at 2V
RMS
Output Level
s
50kHz Maximum Cutoff Frequency
s
Cascadable for Faster Roll-Off
s
Operates from
±
2.375 to
±
8V Power Supplies
s
Self-Clocking with 1 RC
The LTC1065 is the first monolithic filter providing both
clock-tunability with low DC output offset and over 12-bit
DC accuracy. The frequency response of the LTC1065
closely approximates a 5th order Bessel polynomial. With
appropriate PCB layout techniques the output DC offset is
typically 1mV and is constant over a wide range of clock
frequencies. With
±
5V supplies and
±
4V input voltage
range, the CMR of the device is typically 80dB.
The filter cutoff frequency is controlled either by an inter-
nal or external clock. The clock-to-cutoff frequency ratio is
100 : 1. The on-board clock is nearly power supply inde-
pendent and it is programmed via an external RC. The
50
µ
V
RMS
clock feedthrough of the device is considerably
lower than other existing monolithic filters.
The LTC1065 wideband noise is 80
µ
V
RMS
and it can
process large AC input signals with low distortion. With
±
7.5V supplies, for instance, the filter handles up to
4V
RMS
(94dB S/N ratio) while the standard 1kHz THD is
below 0.005%; 87dB dynamic range (S/N + THD) is ob-
tained with input levels between 2V
RMS
and 2.5V
RMS
.
The LTC1065 is available in 8-pin miniDIP and 16-pin SOL.
For a Butterworth response, see LTC1063 data sheet. The
LTC1065 is pin compatible with the LTC1063.
U
S
A
O
PPLICATI
s
Audio
s
Strain Gauge Amplifiers
s
Anti-Aliasing Filters
s
Low Level Filtering
s
Digital Voltmeters
s
Smoothing Filters
s
Reconstruction Filters
V
IN
4.53k
13k*
5V
0.1
µ
F
V
OUT
1065 TA01
SELF-CLOCKING SCHEME
*
200pF*
1
2
3
4
8
7
6
5
LTC1065
0.1
µ
F
5V
4.99k
+
1
µ
F
TANT
Frequency Response
FREQUENCY (kHz)
1
GAIN (dB)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
10
100
1065 TA02
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2
LTC1065
A
U
G
W
A
W
U
W
A
R
BSOLUTE
XI
TI
S
Total Supply Voltage (V
+
to V
–
) .......................... 16.5V
Power Dissipation ............................................. 400mW
Voltage at Any Input .... (V
–
– 0.3V)
≤
V
IN
≤
(V
+
+ 0.3V)
Burn-In Voltage ...................................................... 16V
Storage Temperature Range ................ – 65
°
C to 150
°
C
Operating Temperature Range
LTC1065C .......................................... – 40
°
C to 85
°
C
LTC1065M ....................................... – 55
°
C to 125
°
C
Lead Temperature (Soldering, 10 sec) ................. 300
°
C
W
U
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
NUMBER
LTC1065CN8
LTC1065MJ8
LTC1065CS
T
JMAX
= 150
°
C,
θ
JA
= 100
°
C/ W (J)
T
JMAX
= 100
°
C,
θ
JA
= 110
°
C/ W (N)
T
JMAX
= 100
°
C,
θ
JA
= 85
°
C/ W
ELECTRICAL C
C
HARA TERISTICS
V
S
=
±
5V, f
CLK
= 500kHz, f
C
= 5kHz, R
L
= 10k, T
A
= 25
°
C, unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Clock-to-Cutoff Frequency Ratio (f
CLK
/ f
C
)
±
2.375V
≤
V
S
≤
±
7.5V
100
±
0.5
Maximum Clock Frequency (Note 1)
V
S
=
±
7.5V
5
MHz
V
S
=
±
5V
4
MHz
V
S
=
±
2.5V
3
MHz
Minimum Clock Frequency (Note 2)
±
2.5V
≤
V
S
≤
±
7.5V, T
A
< 85
°
C
30
Hz
Input Frequency Range
0
0.9f
CLK
Filter Gain
V
S
=
±
5V, f
CLK
= 25kHz, f
C
= 250Hz
f
IN
= 250Hz
q
– 3.5
– 3.1
– 2.7
dB
f
IN
= 1kHz
q
– 43.0
– 41.0
– 39.0
dB
V
S
=
±
5V, f
CLK
= 500kHz, f
C
= 5kHz
f
IN
= 100Hz
0
dB
f
IN
= 1kHz = 0.2f
C
q
– 0.215
– 0.175
– 0.135
dB
f
IN
= 2.5kHz = 0.5f
C
q
– 1.1
– 0.972
– 0.84
dB
f
IN
= 4kHz = 0.8f
C
q
– 2.35
– 2.13
– 1.9
dB
f
IN
= 5kHz = f
C
q
– 3.35
– 3.1
– 2.83
dB
f
IN
= 10kHz = 2f
C
q
– 14.63
– 14.15
– 13.7
dB
f
IN
= 20kHz = 4f
C
q
– 43.0
– 41.15
– 39.0
dB
TOP VIEW
S PACKAGE
16-LEAD PLASTIC SOL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
V
IN
GND
NC
V
–
NC
NC
CLK OUT
V
OS
ADJ
NC
V
OUT
NC
V
+
NC
NC
CLK IN
1
2
3
4
8
7
6
5
TOP VIEW
V
IN
GND
V
–
CLK OUT
V
OS
ADJ
V
OUT
V
+
CLK IN
J8 PACKAGE
8-LEAD CERAMIC DIP
N8 PACKAGE
8-LEAD PLASTIC DIP
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3
LTC1065
ELECTRICAL C
C
HARA TERISTICS
V
S
=
±
5V, f
CLK
= 500kHz, f
C
= 5kHz, R
L
= 10k, T
A
= 25
°
C, unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Filter Gain
V
S
=
±
2.375V, f
CLK
= 500kHz, f
C
= 5kHz
f
IN
= 1kHz
q
– 0.225
– 0.185
– 0.145
dB
f
IN
= 2.5kHz
q
– 1.1
– 1.0
– 0.83
dB
f
IN
= 4kHz
q
– 2.35
– 2.15
– 1.9
dB
f
IN
= 5kHz
q
– 3.35
– 3.1
– 2.83
dB
f
IN
= 10kHz
q
– 14.63
–14.1
–13.7
dB
Clock Feedthrough
±
2.375V
≤
V
S
≤
±
7.5V
50
µ
V
RMS
Wideband Noise (Note 3)
±
2.375V
≤
V
S
≤
±
7.5V, 1Hz < f < f
CLK
80
µ
V
RMS
THD + Wideband Noise (Note 4)
V
S
=
±
7.5V, f
C
= 20kHz, f
IN
= 1kHz,
– 87
dB
2V
RMS
≤
V
IN
≤
2.5V
RMS
Filter Output
±
DC Swing
V
S
=
±
2.375V
1.5/– 2.0
1.7/– 2.2
V
q
1.3/– 1.8
V
V
S
=
±
5V
4.0/– 4.5
4.3/– 4.8
V
q
3.8/– 4.3
V
V
S
=
±
7.5V
6.5/– 7.0
6.8/– 7.3
V
q
6.3/– 6.8
V
Input Bias Current
10
nA
Dynamic Input Impedance
800
M
Ω
Output DC Offset (Note 5)
V
S
=
±
2.375V
2
mV
V
S
=
±
5V
0
±
5
mV
V
S
=
±
7.5V
– 4
mV
Output DC Offset Drift
V
S
=
±
2.375V
10
µ
V/
°
C
V
S
=
±
5V
20
µ
V/
°
C
V
S
=
±
7.5V
25
µ
V/
°
C
Self-Clocking Frequency (f
OSC
)
R (Pin 4 to 5) = 20k, C (Pin 5 to GND) = 470pF
V
S
=
±
2.375V
99
103
112
kHz
LTC1065C
q
95
103
112
kHz
LTC1065M
q
92
100
112
kHz
V
S
=
±
5V
100
106
112
kHz
LTC1065C
q
98
106
114
kHz
LTC1065M
q
97
105
114
khz
V
S
=
±
7.5V
102
106
114
kHz
LTC1065C
q
101
109
116
kHz
LTC1065M
q
100
108
116
kHz
External CLK Pin Logic Thresholds
V
S
=
±
2.375V
Min Logical “1”
1.43
V
Max Logical “0”
0.47
V
V
S
=
±
5V
Min Logical “1”
3
V
Max Logical “0”
1
V
V
S
=
±
7.5V
Min Logical “1”
4.5
V
Max Logical “0”
1.5
V
Power Supply Current
V
S
=
±
2.375V, f
CLK
= 500kHz
2.5
4.0
mA
LTC1065C
q
5.5
mA
LTC1065M
q
6.0
mA
V
S
=
±
5V, f
CLK
= 500kHz
5.5
9
mA
LTC1065C
q
11
mA
LTC1065M
q
12
mA
V
S
=
±
7.5V, f
CLK
= 500kHz
7.0
12.0
mA
LTC1065C
q
14.5
mA
LTC1065M
q
16.0
mA
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4
LTC1065
ELECTRICAL C
C
HARA TERISTICS
Output Offset vs Clock,
Medium Clock Rates
Self-Clocking Frequency vs R
Output Offset vs Clock,
Low Clock Rates
EXTERNAL CLOCK FREQUENCY (kHz)
OUTPUT OFFSET (mV)
5
4
3
2
1
0
–1
–2
–3
–4
–5
1065 G03
500
1000
0
V
S
= ±7.5V
V
S
= ±5V
V
S
= ±2.5V
FREQUENCY (kHz)
R PINS 4 TO 5 (k
Ω
)
110
100
90
80
70
60
50
40
30
20
10
1065 G01
100
300
500
LTC1065
R
C
4
5
C = 200pF
f
OSC
≅
1/RC
Gain vs Frequency; V
S
=
±
7.5V
INPUT FREQUENCY (kHz)
1
GAIN (dB)
10
100
1065 G04
B
C
V
IN
= 750mV
RMS
T
A
= 25°C
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
200
A
A. f
CLK
= 0.5MHz
B. f
CLK
= 1MHz
C. f
CLK
= 2MHz
INPUT FREQUENCY (kHz)
1
GAIN (dB)
10
100
1065 G05
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
200
A
B
C
D
A. f
CLK
= 1MHz
B. f
CLK
= 2MHz
C. f
CLK
= 3MHz
D. f
CLK
= 4MHz
V
IN
= 1.4V
RMS
T
A
= 25°C
Gain vs Frequency; V
S
=
±
2.5V
Gain vs Frequency; V
S
=
±
5V
C
C
HARA TERISTICS
U
W
A
TYPICAL PERFOR
CE
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1: The maximum clock frequency is arbitrarily defined as: the
frequency at which the filter AC response exhibits
≥
1dB of gain peaking.
Note 2: At limited temperature ranges (i.e., T
A
≤
50
°
C) the minimum clock
frequency can be as low as 10Hz. The typical minimum clock frequency is
arbitrarily defined as: the clock frequency at which the output DC offset
changes by more than 1mV.
Note 3: The wideband noise specification does not include the clock
feedthrough.
Note 4: To properly evaluate the filter’s harmonic distortion an inverting
output buffer is recommended. An output buffer (although recommended)
is not necessarily needed when measuring output DC offset or wideband
noise (see Figure 3).
Note 5: The output DC offset is optimized for
±
5V supply. The output DC
offset shifts when the power supplies change; however this phenomenon
is repeatable and predictable.
INPUT FREQUENCY (kHz)
1
GAIN (dB)
10
100
1065 G06
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
200
A
B
C
A. f
CLK
= 1MHz
B. f
CLK
= 2MHz
C. f
CLK
= 3MHz
D. f
CLK
= 4MHz
E.f
CLK
= 5MHz
V
IN
= 1.4V
RMS
T
A
= 25°C
E
D
EXTERNAL CLOCK FREQUENCY (Hz)
OUTPUT OFFSET (mV)
50
45
40
35
30
25
20
15
10
5
0
1065 G02
10
110
210
A
B
A. T
A
= 25°C
B. T
A
= 85°C
V
S
= ±5V
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5
LTC1065
Passband Gain and Phase
vs Input Frequency
Power Supply Current vs
Power Supply Voltage
C
C
HARA TERISTICS
U
W
A
TYPICAL PERFOR
CE
THD + Noise vs Input Voltage;
V
S
= Single 5V, AGND = 2V
INPUT (V
RMS
)
0.1
0.001
THD + NOISE (%)
1
5
1065 G07
0.01
0.1
1
A
B
f
IN
= 1kHz, T
A
= 25°C
A. f
C
= 5kHz, f
CLK
= 0.5MHz
B. f
C
= 10kHz, f
CLK
= 1MHz
THD vs Frequency;
V
S
= Single 5V, AGND = 2V
FREQUENCY (kHz)
1
0.001
THD (%)
0.01
0.1
1
2
1065 G08
3
4
5
V
IN
= 0.75V
RMS
,
S/N = 80dB
f
C
= 5kHz, f
CLK
= 500kHz
T
A
= 25°C
THD + Noise vs Input Voltage;
V
S
=
±
7.5V
THD vs Frequency; V
S
=
±
5V
FREQUENCY (kHz)
1
0.001
THD (%)
0.01
0.1
1
10
1065 G10
5
V
IN
= 1.5V
RMS
f
C
= 10kHz, f
CLK
= 1MHz
T
A
= 25°C