LMC1992 Digitally-Controlled Stereo Tone and Volume Circuit with Four-Channel Input-Selector

TL H 10789

LMC1992

Digitally-Controlled

Stereo

Tone

and

Volume

Circuit

with

Four-Channel

Input

Selector

December 1994

LMC1992 Digitally-Controlled Stereo Tone and Volume

Circuit with Four-Channel Input-Selector

General Description

The LMC1992 is a monolithic integrated circuit that provides

four stereo inputs bass and treble tone controls and vol-

ume balance and front-rear fader controls These functions

are digitally controlled through a three-wire communication

interface All of the LMC1992s functions are achieved with

only three external capacitors per channel It is designed for

line level input signals (300 mV

2V) and has a maximum

gain of 0 dB

The internal design is optimized for external capacitors hav-

ing values of 0 1 mF or less This allows the use of chip

capacitors for coupling and tone control functions

Low noise and distortion result from using analog switches

and thin-film silicon-chromium resistor networks in the sig-

nal path

Volume and fader are at minimum and tone controls are flat

when supply voltage is first applied

Additional tone control can be achieved using the LMC835

stereo

7-band

graphic

equalizer

connected

the

LMC1992’s select-out select-in external processor loop

Features

Low noise and distortion

Four stereo inputs

40 volume levels including mute

20 fader levels

All attenuators have a 2 dB of attenuation per step

Front back fade control

External processor loop

Only three external components per channel

Serial programmable standard MICROWIRE

interface

Single supply operation 6V to 12V supply voltage

Protection address (similar to DS8906)

DC-coupled inputs

Single supply operation

Applications

Automotive audio systems

Sound reinforcement systems

Home entertainment

stereo television and music re-

production systems

Electronic music (MIDI)

Block and Connection Diagrams

TL H 10789 – 1

Left channel shown Pin numbers in parentheses are for the right channel

TL H 10789 – 2

Order Number LMC1992CCN

See NS Package Number N28B

DNR

is a registered trademark of National Semiconductor Corporation

COPS

and MICROWIRE

are trademarks of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M75 Printed in U S A

Absolute Maximum Ratings

(Notes 1 and 2)

If Military Aerospace specified devices are required

please contact the National Semiconductor Sales

Office Distributors for availability and specifications

Supply Voltage (V

GND)

15V

Voltage at Any Pin

GND

0 2V to V

0 2V

Input Current at Any Pin (Note 3)

5 mA

Package Input Current (Note 3)

20 mA

Power Dissipation (Note 4)

500 mW

Junction Temperature

125 C

Storage Temperature

65 C to

150 C

Lead Temperature

N Package Soldering 10 sec

260 C

ESD Susceptibility (Note 5)

2000V

Pins 9 10 11 19 20 21

850V

Operating Ratings

(Notes 1 and 2)

Temperature Range

MIN

MAX

LMC1992CCN

0 C

70 C

Supply Voltage Range (V

)

6V to 12V

Electrical Characteristics

The following specifications apply for V

8V f

1 kHz input signal applied to

channel 1 volume

0 dB bass

0 dB treble

0 dB and faders

0 dB unless otherwise specified All limits T

25 C

Symbol

Parameter

Conditions

Typical

Limit

Units

(Note 6)

(Note 7)

(Limit)

Supply Current

27 0

mA (max)

Input Voltage

Clipping Level (1 0% THD)

2 3

2 0

rms

(min)

Select Out (Pins 8 22)

OUT

Output Voltage

Clipping Level (1 0% THD)

1 2

0 65

rms

(min)

Outputs (Pins 13 14 16 17)

THD

Total Harmonic Distortion

All Four Channels

Volume Attenuator at 0 dB Input Level 0 3 V

rms

0 15

0 3

% (max)

Volume Attenuator at

20 dB Input Level 0 6 V

rms

0 03

0 1

% (max)

nOUT

Output Noise

All Four Channels CCIR ARM Filter R

6 5

30 0

rms

(max)

nOUT

Output Noise

All Four Channels CCIR ARM Filter R

5 0

20 0

rms

(max)

Volume Attenuator

e b

80 dB

OUT

DC Output Impedance

Pins 8 22

100

150

(max)

Pins 13 14 16 17

120

(max)

DC Input Impedance

Pins 4 5 6 7 23 24 25 26

Volume Attenuator Range

Pins 16 17 Volume Attenuation at

0101110100X (0 dB) (Absolute Gain)

1 0

1 5

dB (max)

01011000000 (80 dB) (Relative to Attenuation at

80 0

75 0

dB (min)

the 0 dB setting)

Volume Step Size

All Volume Attenuation Settings from 01011001010

2 0

0 7

dB (min)

(60 dB) to 0101110100X (0 dB) (Note 9)

4 3

dB (max)

Channel-to-Channel Volume

Fader Attenuation from 1XXX000000

0 5

1 0

dB (max)

Tracking Error

(40 dB) to 1XXX1010X (0 dB)

Fader Attenuation Range

Pins 16 17 Fader Attenuation at

011XXX1010X (0 dB) (Absolute Gain)

1 0

1 5

dB (max)

011XXX00000 (40 dB) (Relative to Attenuation at

38 0

dB (min)

the 0 dB setting)

Fader Step Size

All Fader Attenuation Settings from 011XXX00000

2 0

1 0

dB (min)

(40 dB) to 011XXX1010X (0 dB) (Note 10)

4 5

dB (max)

Electrical Characteristics

The following specifications apply for V

8V f

1 kHz input signal applied to

channel 1 volume

0 dB bass

0 dB treble

0 dB and faders

0 dB unless otherwise specified All limits T

25 C (Continued)

Symbol

Parameter

Conditions

Typical

Limit

Units

(Note 6)

(Note 7)

(Limit)

Bass Gain Range

100 Hz Pins 14 16

10 0

dB (min)

Bass Tracking Error

100 Hz Pins 14 16

0 1

1 0

dB (max)

Bass Step Size

100 Hz Pins 14 16

2 0

1 0

dB (min)

(Relative to Previous Level)

3 0

dB (max)

Treble Gain Range

10 kHz Pins 14 16

10 0

dB (min)

Treble Tracking Error

10 kHz Pins 14 16

0 1

1 0

dB (max)

Treble Step Size

10 kHz Pins 14 16

2 0

1 0

dB (min)

(Relative to Previous Level)

3 0

dB (max)

Frequency Response

3 dB

450

kHz

0 3 dB (Relative to Signal Amplitude at 1 kHz)

kHz (min)

Channel Separation

1 0 V

rms

dB (min)

Input-Input Isolation

1 0 V

rms

(Note 8)

dB (min)

PSRR

Power Supply Rejection Ratio

8 V

100 mV

P-P

dB (min)

100 Hz Sinewave Applied to Pin 28

CLK

Clock Frequency

1 0

0 5

MHz (max)

IN(1)

Logic ‘‘1’’ Input Voltage

1 3

2 0

V (min)

IN(0)

Logic ‘‘0’’ Input Voltage

0 4

0 8

V (max)

Note 1

Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is

functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed

specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test

conditions

Note 2

All voltages are specified with respect to ground

Note 3

When the input voltage (V

) at any pin exceeds the power supply voltages (V

or V

) the absolute value of the current at that pin should be

limited to 5 mA or less The 20 mA package input current limits the number of pins that can exceed the power supply voltages with 5 mA current limit to four

Note 4

The maximum power dissipation must be de-rated at elevated temperatures and is dictated by T

JMAX

and the ambient temperature T

The maximum

allowable power dissipation is PD

JMAX

) i

or the number given in the Absolute Maximum Ratings whichever is lower For the LMC1992CCN T

JMAX

125 C and the typical junction-to-ambient thermal resistance when board mounted is 67 C W

Note 5

Human body model 100 pF discharged through a 1 5 kX resistor

Note 6

Typicals are at T

25 C and represent the most likely parametric norm

Note 7

Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)

Note 8

The Input-Input Isolation is tested by driving one input and measuring the front outputs when the undriven inputs are selected

Note 9

The Volume Step Size is defined as the change in attenuation between any two adjacent volume attenuation settings The nominal Volume Step Size is

2 dB

Note 10

The Fader Step Size is defined as the change in attenuation between any two adjacent fader attenuation settings The nominal Volume Step Size is 2 dB

Pin Description

DATA(1)

This is the serial data input for communica-

tions sent by a controller The data rate has a

maximum

frequency

500

kHz

The

LMC1992 requires 11 bits of data to control

or change a function the first two bits a 1

and 0 select the LMC1992 the next three

bits select a function and the final six bits set

the function to a desired value The data

must be valid on the rising edge of the

CLOCK input signal

CLOCK(2)

The CLOCK input accepts a TTL or CMOS

level clocking signal The input is used to

clock the DATA input signal and determines

when a data bit is valid

ENABLE(3)

This input accepts a logic low signal when a

controller is addressing the LMC1992 When

ENABLE is active the LMC1992 responds to

input signals present on the DATA and

CLOCK inputs

INPUT 1 – 4

Four two-channel analog inputs are available

(4 – 7 23 – 26) on the LMC1992 These pins should be dc-bi-

ased to mid-supply

SELECT OUT The selected INPUT signal is available at this

(8 22)

output This feature allows the use of external

signal processing such as noise reduction or

graphic equalizers This output can typically

sink 1 mA

SELECT IN

This is the input that an external signal proc-

(9 21)

essor uses to return a signal to the LMC1992

TONE IN

This is the input to the tone control amplifier

(10 20)

See the Application Information section titled

‘‘Tone Control Response’’

TONE OUT

Tone control amplifier output See the Appli-

(11 19)

cation Information section titled ‘‘Tone Con-

trol Response’’

OP AMP OUT This output is used externally with the tone

(12 18)

control capacitors Internally this output is

applied to the volume attenuators

REAR OUT

This pin’s output signal is intended for the

(13 17)

rear amplifiers in a four speaker stereo sys-

tem The output can typically sink 350 mA

FRONT OUT This pin’s output signal is intended for the

(14 16)

front amplifiers in a four speaker stereo sys-

tem The output can typically sink 350 mA

GROUND

(15)

This is the system ground connection

(28)

This is the power supply connection The

LMC1992 is operational with supply voltages

from 6V to 12V It is recommended that this

pin is bypassed with 0 1 mF capacitor

BYPASS (27) A 10 mF capacitor is connected between this

pin and ground

General Information

The LMC1992 is a CMOS bipolar high quality building block

intended for high fidelity audio signal processing It is de-

signed for line level input signals (300 mV

2V) and has a

maximum gain of

1 dB While the LMC1992 is manufac-

tured with CMOS processing NPN transistors are used to

build low noise op amps

The combination of CMOS

switches bipolar op amps and SiCr resistors make it possi-

ble to achieve an order of magnitude quality improvement

over other bipolar circuits that use analog multipliers to ac-

complish gain adjustment

The LMC1992 has internal decoding logic that allows a

computer (mP) to communicate directly to the audio control

circuitry through a standard MICROWIRE interface This

three-wire interface consists of a DATA input line a CLOCK

input line and an ENABLE line When the ENABLE line is

low data can be serially shifted from the controller to the

LMC1992 As the ENABLE line goes through the low-to-

high transition any additional data is ignored Data present

in the internal shift register is latched and the instruction is

executed

Figure 1 shows the connection diagram of a typical

LMC1992 application

TL H 10789 – 18

FIGURE 1 Typical Connection Diagram

Applications Information

MINIMUM LOAD IMPEDANCE

The LMC1992 employs emitter-follower buffers at pins 8

and 22 (SELECT OUT) 13 and 14 (LEFT FRONT and

REAR OUTPUTs) and 16 and 17 (RIGHT FRONT-and-

REAR OUTPUTs) that buffer output signals Typical bias

current of 1 mA is used for the SELECT OUTPUT buffers

and 350 mA for the LEFT-and-RIGHT FRONT-and-REAR

OUTPUT buffers

The Electrical Specifications table lists a maximum input sig-

nal of 2 3 V

rms

(3 25 V

peak

) for 1% THD at the SELECT

OUT pins This distortion level is achieved when the mini-

mum ac load impedance seen by the SELECT OUT pin is

3 25 kX (3 25V 1 mA) For the LEFT-and-RIGHT FRONT-

and-REAR OUTPUTs the typical maximum output is 1 2

rms

(1 55 V

peak

) Therefore the minimum load impedance

is 4 43 kX (1 55 V 0 35 mA) Trying to use a lower imped-

ance results in a clipped output signal Therefore

the

chance of clipping can be greatly reduced and much lower

distortion levels can be achieved by using load impedances

that are an order of magnitude higher than shown here

For applications that require dc coupling and the INPUTs

biased to V

2 the minimum load impedance will differ

from that detailed in the above discussion The emitter fol-

lowers may be potentially operating at high currents be-

cause there is a dc voltage V

0 7V at the SELECT

OUT pins dc resistance to ground will result in increased

current flow Latch-up may occur if the total emitter current

exceeds 5 mA This current is a combination of the emitter

follower’s 1 mA current source and 4 mA drawn by the ex-

ternal load Therefore to prevent this possibility the mini-

mum dc load impedance should be

peak

0 7V)

4 mA

1638X

peak

3 25V

To allow for variations and part tolerances 2 0 kX is a good

choice for this minimum dc load impedance

When dc coupling is used at the LEFT-and-RIGHT FRONT-

and-REAR OUTPUTs the output emitter followers will be

operating at a nominal dc voltage of V

2(0 7V)

Latch-up may occur if the total emitter current exceeds

1 mA This current is a combination of the emitter follower’s

0 35 mA current source and 0 65 mA drawn by the external

load Therefore to prevent this possibility the minimum dc

load impedance should be

peak

2(0 7V))

0 65 mA

9 kX

peak

3 25V

TL H 10789 – 20

FIGURE 2 Input Bias Network

To allow for variations and part tolerances 10 kX is a good

choice for this minimum dc load impedance

INPUT IMPEDANCE

For ac coupled input signals the input impedance value is

determined by bias resistor R1 as shown in

Figure 2 A

directly coupled input signal will see an emitter follower’s

nominal input impedance of 2 MX

The SELECT IN pins have an input impedance that varies

with the BASS and TREBLE control settings The input im-

pedance is 96 kX at dc and 27 kX at 1 kHz when the con-

trols are set at 0 dB Minimum input impedance of 28 kX at

dc and 24 kX at 1 kHz occurs when maximum boost is

selected At 10 kHz the minimum input impedance with the

tone controls flat is 8 kX and with the tone controls at

maximum boost is 3 kX

STEREO SIGNAL INPUTS

When operating with a single supply voltage the stereo sig-

nal inputs must be dc biased to one-half of the supply volt-

age as shown in

Figure 2 As an example with a supply

voltage of 8V all signal sources should have a dc bias of

4V The maximum input signal level of 6 5 V

p-p

(for 1%

THD) would then swing from 0 75V to 7 25V Input-to-input

crosstalk can be minimized by using a separate dc bias cir-

cuit for each stereo input pair

EXTERNAL SIGNAL PROCESSING

The signal present at the selected input will be available at

the SELECT OUT pins 8 (left) and 22 (right) The dc bias

voltage at those pins will be one base-emitter voltage ap-

proximately 0 7 V

below the source because of the inter-

nal emitter follower Therefore if the selected input has a

bias of 4 0 V

the dc component at pins 8 and 22 will be

about 3 3 V

The LMC1992’s SELECT OUT emitter followers allow addi-

tional signal sources using emitter follower outputs (such as

multiple LMC1992s) to be ‘‘wired-ORed’’ together When

this feature is in use the input channel of the LMC1992 not

in use should be set to ‘‘open’’ input codes 01000XX0000 or

01000XX011X

Applications Information

(Continued)

TL H 10789 – 19

FIGURE 3 System Block Diagram Showing Inclusion of DNR

Noise

Reduction (LM1894) and Equalizer (LMC835) (One Channel Only

LMC1992)

The SELECT OUT pins (8 and 22) enable greater system

design flexibility by providing a means to implement an ex-

ternal processing loop This loop can be used for noise re-

duction circuits such as DNR (LM1894) or mulit-band graph-

ic equalizers (LMC835) It is important to ensure that if both

are used the noise reduction circuitry precede the equaliza-

tion circuits Failure to do so will result in improper operation

of the noise reduction circuits The system shown in

Figure

3 utilizes the external loop to include DNR and a multi-band

equalizer

AUDIO MUTE

A mute function with attenuation of 100 dB is possible with

the volume control set to

80 dB and the INPUT select

code set to 01000XX0000 (open circuit)

TONE CONTROL RESPONSE

Base and treble tone controls are included in the LMC1992

The tone controls use just two external capacitors for each

stereo channel Each has a corner frequency determined by

the value of C2 and C3

(Figure 4) and internal resistors in

the feedback loop of the internal tone amplifier The maxi-

mum amplitude boost or cut is determined by the data sent

to the LMC1992 (see Table I)

The typical tone control response shown in the Typical Per-

formance Curves were generated with C2

0 0082 mF and show the response for each step When

modifying the tone control response it is important to note

that the ratio of C3 and C2 sets the mid-frequency gain

Symmetrical tone response is achieved when C2

However with C2

2(C3) and the tone controls set to

‘‘flat’’ the frequency response will be flat at 20 Hz and 20

kHz and

6 dB at 1 kHz

The frequency where a tone control begins to deviate from

a flat response will be referred to as the turn-over frequen-

cy With C

C3 the LMC1992’s treble turn-over

frequency is nominally

C(14 2 kX)

The base turn-over frequency is nominally

C(27 7 kX)

when maximum boost is chosen The inflection points (the

frequencies where the boost or cut is within 3 dB of the final

value) are for treble and bass

C(2 3 kX)

C(164 1 kX)

Applications Information

(Continued)

TL H 10789 – 22

FIGURE 4 The Tone Control Amplifier

Increasing the values of C2 and C3 decreases the turnover

and inflection frequencies i e the Tone Control Response

Curves shown in Typical Performance Curves will shift left

when C2 and C3 are increased and shift right when C2 and

C3 are decreased With C2

0 0082 2 dB steps are

achieved at 100 Hz and 10 kHz Changing C2 and C3 to

0 01 mF shifts the 2 dB per step frequency to 72 Hz and 8 3

kHz If the tone control capacitors’ size is decreased these

frequencies will increase With C2

0 0068 mF the 2

dB steps take place at 130 Hz and 11 2 kHz

FADER FUNCTION

The four fader functions are all independently adjustable

and therefore no balance control is needed Emulating a

balance control is accomplished through software by simul-

taneously changing a channel’s front and rear faders by

equal amounts To satisfy normal balance requirements the

faders have an attenuation range of 40 dB

SERIAL COMMUNICATION INTERFACE

Figure 5 shows the LMC1992’s timing diagram for its three

wire MICROWIRE interface A controller’s data stream can

be any length once the correct device address is received

by the LMC1992 any number of data bits can be sent the

last nine bits occurring before ENABLE goes high are used

by the LMC1992 The first two bits in a valid data stream are

decoded and used as device address bits The LMC1992

uses a unique address of 1 0 The LMC1992 will not re-

spond to information on the DATA line if any other address

is used This allows other MICROWIRE serially programma-

ble devices to share the same three-wire communication

bus When ENABLE goes high any further serial data is

ignored and the contents of the shift register is transferred

to the data latches Only when information is received by

the data latches do any function or setting changes take

place

The first three of nine bits select one of the

LMC1992s functions The remaining six bits set the select-

ed function to the desired value or position

A data bit is accepted as valid and clocked into an internal

shift register on each rising edge of the signal appearing at

the LMC1992s CLOCK input pin Proper data interpretation

and operation is ensured when ENABLE makes its falling

transition during the time when CLOCK is low Erroneous

operation will result if the ENABLE signal makes its falling

transition at any other time

TL H 10789 – 21

Note 1

Negative transition on ENABLE clears previous address Clock must be low during transition

Note 2

Additional don’t care states may be inserted here for ease of programming (Optional )

Note 3

Positive transition on ENABLE latches in new data if the LMC1992 has been addressed Clock can either be high or low during transition

FIGURE 5 Clocking Data into the Standard MICROWIRE Interface

(Minimum Number of Bits in Data Stream)