TL F 10721
DS3885
BTL
Arbitration
Transceiver
January 1994
DS3885 BTL Arbitration Transceiver
General Description
The DS3885 is one in a series of transceivers designed spe-
cifically for the implementation of high performance Future-
bus
a
and proprietary bus interfaces The DS3885 Arbitra-
tion Transceiver is designed to conform to IEEE 1194 1
(Backplane Transceiver Logic
BTL) as specified in the
IEEE 896 2 Futurebus
a
specification
The Arbitration
Transceiver incorporates the competition logic internally
which simplifies the implementation of a Futurebus
a
appli-
cation by minimizing the on board logic required
The DS3885 driver output configuration is an NPN open col-
lector which allows Wired-OR connection on the bus Each
driver output incorporates a Schottky diode in series with its
collector to isolate the transistor output capacitance from
the bus thus reducing the bus loading in the inactive state
The BTL drivers also have high sink current capability to
comply with the bus loading requirements defined within
IEEE 1194 1 BTL specification
Backplane Transceiver Logic (BTL) is a signaling standard
that was invented and first introduced by National Semicon-
(Continued)
Features
Y
9-bit inverting BTL transceiver
Y
Meets IEEE 1194 1 standard on Backplane Transceiver
Logic (BTL)
Y
Includes on chip competition logic and parity checking
Y
Supports live insertion
Y
Glitch free power-up down protection
Y
Typically less than 5 pF bus-port capacitance
Y
Low bus-port voltage swing (typically 1V) at 80 mA
Y
Open collector bus-port output allows Wired-OR
connection
Y
Exceeds 2 kV ESD testing (Human Body Model)
Y
Individual bus-port ground pins minimize ground bounce
Y
Controlled rise and fall time to reduce noise coupling to
adjacent lines
Y
TTL compatible driver and control inputs
Y
Built in bandgap reference with separate QV
CC
and
QGND pins for precise receiver thresholds
Y
Product offered in PLCC and PQFP package styles
Connection Diagrams
TL F 10721 – 2
TL F 10721 – 13
Order Number DS3885V or DS3885VF
See NS Package Number V44A or VF44B
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M75 Printed in U S A
General Description
(Continued)
ductor then developed by the IEEE to enhance the per-
formance of backplane buses BTL compatible transceivers
feature low output capacitance drivers to minimize bus load-
ing a 1V nominal signal swing for reduced power consump-
tion and receivers with precision thresholds for maximum
noise immunity BTL eliminates settling time delays that se-
verely limit TTL bus performance and thus provide signifi-
cantly higher bus transfer rates The backplane bus is in-
tended to be operated with termination resistors (selected
to match the bus impedance) connected to 2 1V at both
ends The low voltage is typically 1V
Separate ground pins are provided for each BTL output to
minimize induced ground noise during simultaneous switch-
ing
The transceiver’s control and driver inputs are designed
with high impedance PNP input structures and are fully TTL
compatible
The receiver is a high speed comparator that utilizes a
bandgap reference for precision threshold control allowing
maximum noise immunity to the BTL 1V signaling level
Separate QV
CC
and QGND pins are provided to minimize
the effects of high current switching noise The output is
TRI-STATE
and fully TTL compatible
The signals ab
k
7 0
l
designate the arbitration bus number
which this transceiver places on the bus The signal names
AB
k
7 0
l
designate the open collector Wired-OR signals
on the backplane bus
The DS3885 implements an odd parity check on the arbitra-
tion bus bits AB
k
7 0
l
with ABP being the parity bit The
signal PER will indicate the parity check result For a quick
indication of current bus conditions the bus status block
generates ALL1 (all asserted) status when all bits
(AB
k
7 0
l
) are asserted by any module This signal is used
by the DS3875 Arbitration Controller to detect the Arbitra-
tion message number (during phase 1) or the powerfail mes-
sage number (during phase 2)
To latch the arbitration number into the transceiver it is
placed onto the CN
k
7 0
l
port and the CN
LE signal is
asserted When the CMPT signal is asserted the arbitration
number is placed on the bus lines AB
k
7 0
l
The WIN
GT
signal serves two purposes during the arbitration cycle If
the CMPT signal is not asserted during the arbitration cycle
the transceiver compares its internally latched number to
the number on the AB
k
7 0
l
bus lines If the internal num-
ber on the transceiver is greater than or equal to the number
on the AB
k
7 0
l
lines the WIN
GT signal is asserted
However if the CMPT signal is asserted the transceiver
participates in the competition If the transceiver wins the
arbitration the WIN
GT signal is asserted to confirm the
winning The AB
RE signal is used to enable the on-chip
receiver outputs
The DS3885 supports live insertion as defined in IEEE
896 2 through the LI (Live Insertion) pin To implement live
insertion the LI pin should be connected to the live insertion
power connector If this function is not supported the LI pin
must be tied to the V
CC
pin The DS3885 also provides
glitch free power-up down protection during power se-
quencing
The DS3885 has two types of power connections in addition
to the LI pin They are the Logic V
CC
(V
CC
) and the Quiet
V
CC
(QV
CC
) There are two V
CC
pins on the DS3885 that
provide the supply voltage for the logic and control circuitry
Multiple power pins reduce the effects of package induc-
tance and thereby minimize switching noise As these pins
are common to the V
CC
bus internal to the device a voltage
difference should never exist between these pins and the
voltage difference between V
CC
and QV
CC
should never
exceed
g
0 5V because of ESD circuitry
Additionally the ESD circuitry between the V
CC
pins and all
other pins except for BTL I O’s and LI pins requires that any
voltage on these pins should not exceed the voltage on V
CC
a
0 5V
There are three different types of ground pins on the
DS3885 They are the logic ground (GND) BTL grounds
(AB0GND – AB7GND ABPGND) and the Bandgap refer-
ence ground (QGND) All of these reference pins are isolat-
ed within the chip to minimize the effects of high current
switching transients For optimum performance the QGND
should be returned to the connector through a quiet channel
that does not carry transient switching current The GND
and AB0GND – AB7GND ABPGND should be connected to
the nearest backplane ground pin with the shortest possible
path
Since many different grounding schemes could be imple-
mented and ESD circuitry exists on the DS3885 it is impor-
tant to note that any voltage difference between ground
pins QGND GND or AB0GND – AB7GND and ABPGND
should not exceed
g
0 5V including power-up down se-
quencing
Three additional transceivers are included in the Future-
bus
a
family They are the DS3883A BTL 9-bit Transceiver
The DS3884A BTL Handshake Transceiver features select-
able Wired-OR glitch filtering The DS3886A BTL 9-bit
Latching Data Transceiver contains edge triggered latches
in the driver which may be bypassed during a fall-through
mode In addition the device contains a transparent latch in
the receiver section
The DS3875 Arbitration Controller included in the Future-
bus
a
family supports all the required and optional modes
for Futurebus
a
arbitration protocol It is designed to be
used in conjunction with the DS3884A and DS3885 trans-
ceivers
The LOGICAL INTERFACE FUTUREBUS
a
ENGINE (LIFE)
is a high performance Futurebus
a
Protocol Controller de-
signed for IEEE 896 1 The LIFE will handle all handshaking
signals between the Futurebus
a
and the local bus inter-
face The Protocol Controller supports the Futurebus
a
compelled mode data transfer as both master and slave
The Protocol Controller can be configured to operate in
compliance to IEEE 896 2 Profile B mode The LIFE incor-
porates a DMA controller and 64-bit FIFO’s for fast queuing
All of the transceivers are offered in 44-pin PLCC and PQFP
high density package styles
2
