��

San 16 Banwol-Ri

Taean-Eup Hwasung- City

Kyungki Do, Korea

Tel.) 82 - 31 - 208 - 6463

Fax.) 82 - 31 -208 - 6799

March. 2003

ELECTRONICS

512Mb/256Mb 1.8V NAND Flash Errata

Description : Some of AC characteristics are not meeting the specification

> AC characteristics : Refer to Table

Affected Products : K9F1208Q0A-XXB0, K9F1216Q0A-XXB0

K9F5608Q0C-XXB0, K9F5616Q0C-XXB0

K9K1208Q0C-XXB0, K9K1216Q0C-XXB0

Improvement schedule : The components without this restriction will

be available from work week 23 or after.

Workaround : Relax the relevant timing parameters according to the table.

Sincerely,

chwoosun@sec.samsung.com

Product Planning & Application Eng.

Memory Division

Samsung Electronics Co.

Table

Parameters

Specification

Relaxed Condition

tWC

tWH

tWP

tRC

tREH

tRP

tREA

UNIT : ns

tCEA

K9F1216U0A-YCB0,YIB0,PCB0,PIB0

FLASH MEMORY

K9F1216U0A-DCB0,DIB0,HCB0,HIB0

K9F1208U0A-YCB0,YIB0,PCB0,PIB0

K9F1208U0A-DCB0,DIB0,HCB0,HIB0

K9F1208Q0A-DCB0,DIB0,HCB0,HIB0

K9F1216Q0A-DCB0,DIB0,HCB0,HIB0

K9F1208U0A-VCB0,VIB0,FCB0,FIB0

Document Title

64M x 8 Bit , 32M x 16 Bit NAND Flash Memory

Revision History

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near you.

Revision No.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Remark

Preliminary

History

Initial issue.

TBGA(K9F12XXX0A-DCB0/DIB0) size information is changed.

(before) 9 x 11 /0.8mm pitch , Width 1.0 mm

(after ) To Be Decided.

TBGA(K9F12XXX0A-DCB0/DIB0) size information is changed.

(before) 9 x 11 /0.8mm pitch , Width 1.0 mm, to

(after) 8.5 x 15 /0.8mm pitch, Width 1.0mm

Pin numbering includes TBGA Dummy ball . (Page5)

Pin numbering excludes TBGA Dummy ball . (Page5)

Pin assignment of TBGA dummy ball is changed.

(before) DNU --> (after) N.C

1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 43)

2. Add the data protection Vcc guidence for 1.8V device - below about

1.1V. (Page 44)

The min. Vcc value 1.8V devices is changed.

K9F12XXQ0A : Vcc 1.65V~1.95V --> 1.70V~1.95V

Pb-free Package is added.

K9F1208U0A-FCB0,FIB0

K9F1208Q0A-HCB0,HIB0

K9F1216U0A-HCB0,HIB0

K9F1216U0A-PCB0,PIB0

K9F1216Q0A-HCB0,HIB0

K9F1208U0A-HCB0,HIB0

K9F1208U0A-PCB0,PIB0

Errata is added.(Front Page)-K9F12XXQ0A

tWC tWH tWP tRC tREH tRP tREA tCEA

Specification 45 15 25 50 15 25 30 45

Relaxed value 60 20 40 60 20 40 40 55

New definition of the number of invalid blocks is added.

(

Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb

memory space.

)

Draft Date

Apr. 25th 2002

May. 9th 2002

July, 10th 2002

Aug, 10th 2002

Oct, 21th 2002

Nov, 21th 2002

Mar. 5th 2003

Mar. 13rd 2003

Mar. 17th 2003

Apr. 4th 2003

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.

http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html

K9F1216U0A-YCB0,YIB0,PCB0,PIB0

FLASH MEMORY

K9F1216U0A-DCB0,DIB0,HCB0,HIB0

K9F1208U0A-YCB0,YIB0,PCB0,PIB0

K9F1208U0A-DCB0,DIB0,HCB0,HIB0

K9F1208Q0A-DCB0,DIB0,HCB0,HIB0

K9F1216Q0A-DCB0,DIB0,HCB0,HIB0

K9F1208U0A-VCB0,VIB0,FCB0,FIB0

GENERAL DESCRIPTION

FEATURES

•

Voltage Supply

- 1.8V device(K9F12XXQ0A) : 1.70~1.95V

- 3.3V device(K9F12XXU0A) : 2.7 ~ 3.6 V

•

Organization

- Memory Cell Array

- X8 device(K9F1208X0A) : (64M + 2048K)bit x 8 bit

- X16 device(K9F1216X0A) : (32M + 1024K)bit x 16bit

- Data Register

- X8 device(K9F1208X0A) : (512 + 16)bit x 8bit

- X16 device(K9F1216X0A) : (256 + 8)bit x16bit

•

Automatic Program and Erase

- Page Program

- X8 device(K9F1208X0A) : (512 + 16)Byte

- X16 device(K9F1216X0A) : (256 + 8)Word

- Block Erase :

- X8 device(K9F1208X0A) : (16K + 512)Byte

- X16 device(K9F1216X0A) : ( 8K + 256)Word

•

Page Read Operation

- Page Size

- X8 device(K9F1208X0A) : (512 + 16)Byte

- X16 device(K9F1216X0A) : (256 + 8)Word

- Random Access : 12

s(Max.)

- Serial Page Access : 50ns(Min.)

64M x 8 Bit / 32M x 16 Bit NAND Flash Memory

•

Fast Write Cycle Time

- Program time : 200

s(Typ.)

- Block Erase Time : 2ms(Typ.)

•

Command/Address/Data Multiplexed I/O Port

•

Hardware Data Protection

- Program/Erase Lockout During Power Transitions

•

Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

•

Command Register Operation

•

Intelligent Copy-Back

•

Unique ID for Copyright Protection

•

Package

- K9F12XXU0A-YCB0/YIB0

48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)

- K9F12XXX0A-DCB0/DIB0

63- Ball TBGA

- K9F1208U0A-VCB0/VIB0

48 - Pin WSOP I (12X17X0.7mm)

- K9F12XXU0A-PCB0/PIB0

48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package

- K9F12XXX0A-HCB0/HIB0

63- Ball TBGA - Pb-free Package

- K9F1208U0A-FCB0/FIB0

48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package

* K9F1208U0A-V,F(WSOPI ) is the same device as

K9F1208U0A-Y,P(TSOP1) except package type.

Offered in 64Mx8bit or 32Mx16bit, the K9F12XXX0A is 512M bit with spare 16M bit capacity. The device is offered in 1.8V or 3.3V

Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be

performed in typical 200

s on the 528-byte(X8 device) or 264-word(X16 device) page and an erase operation can be performed in

typical 2ms on a 16K-byte(X8 device) or 8K-word(X16 device) block. Data in the page can be read out at 50ns cycle time per word.

The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write control automates all

program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the

write-intensive systems can take advantage of the K9F12XXX0A

′

s extended reliability of 100K program/erase cycles by providing

ECC(Error Correcting Code) with real time mapping-out algorithm.

The K9F12XXX0A is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable

applications requiring non-volatility.

PRODUCT LIST

Part Number

Vcc Range

Organization

PKG Type

K9F1208Q0A-D,H

1.70 ~ 1.95V

TBGA

K9F1216Q0A-D,H

X16

K9F1208U0A-Y,P

2.7 ~ 3.6V

TSOP1

K9F1208U0A-D,H

TBGA

K9F1208U0A-V,F

WSOP1

K9F1216U0A-Y,P

X16

TSOP1

K9F1216U0A-D,P

TBGA

K9F1216U0A-YCB0,YIB0,PCB0,PIB0

FLASH MEMORY

K9F1216U0A-DCB0,DIB0,HCB0,HIB0

K9F1208U0A-YCB0,YIB0,PCB0,PIB0

K9F1208U0A-DCB0,DIB0,HCB0,HIB0

K9F1208Q0A-DCB0,DIB0,HCB0,HIB0

K9F1216Q0A-DCB0,DIB0,HCB0,HIB0

K9F1208U0A-VCB0,VIB0,FCB0,FIB0

PIN CONFIGURATION (TSOP1)

K9F12XXU0A-YCB0,PCB0/YIB0,PIB0

N.C

R/B

N.C

Vcc

Vss

N.C

CLE

ALE

N.C

Vss

I/O15

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

N.C

Vcc

N.C

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

Vss

N.C

R/B

N.C

Vcc

Vss

N.C

CLE

ALE

N.C

I/O7

I/O6

I/O5

I/O4

N.C

Vcc

Vss

N.C

I/O3

I/O2

I/O1

I/O0

N.C

X16

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

48 - TSOP1 - 1220F

Unit :mm/Inch

0.787

0.008

20.00

0.20

#24

-0

#48

#25

(

)

0.039

0.002

1.00

0.05

0.002

0.05

MIN

0.047

1.20

MAX

0.45~0.75

0.018~0.030

0.724

0.004

18.40

0.10

0~8

¡Æ

-0

0.50

0.020

(

)

K9F1216U0A-YCB0,YIB0,PCB0,PIB0

FLASH MEMORY

K9F1216U0A-DCB0,DIB0,HCB0,HIB0

K9F1208U0A-YCB0,YIB0,PCB0,PIB0

K9F1208U0A-DCB0,DIB0,HCB0,HIB0

K9F1208Q0A-DCB0,DIB0,HCB0,HIB0

K9F1216Q0A-DCB0,DIB0,HCB0,HIB0

K9F1208U0A-VCB0,VIB0,FCB0,FIB0

K9F12XXX0A-DCB0,HCB0/DIB0,HIB0

R/B

/WE

/CE

Vss

ALE

/WP

/RE

CLE

NC Vcc

NC I/O0

I/O1

NC VccQ I/O5 I/O7

Vss

I/O6

I/O4

I/O3

I/O2

Vss

N.C

N.C N.C

N.C

N.C N.C

N.C

N.C N.C

N.C

N.C N.C

N.C

N.C N.C

N.C

N.C N.C

N.C

N.C N.C

N.C

N.C N.C

N.C

R/B

/WE

/CE

Vss

ALE

/WP

/RE

CLE

I/O7

I/O5

I/O12 IO14

Vcc

I/O10

I/O8 I/O1

I/O9

I/O0

I/O3 VccQ I/O6 I/O15

Vss

I/O13

I/O4

I/O11

I/O2

Vss

X16

PIN CONFIGURATION (TBGA)

1 2

Top View

K9F1216U0A-YCB0,YIB0,PCB0,PIB0

FLASH MEMORY

K9F1216U0A-DCB0,DIB0,HCB0,HIB0

K9F1208U0A-YCB0,YIB0,PCB0,PIB0

K9F1208U0A-DCB0,DIB0,HCB0,HIB0

K9F1208Q0A-DCB0,DIB0,HCB0,HIB0

K9F1216Q0A-DCB0,DIB0,HCB0,HIB0

K9F1208U0A-VCB0,VIB0,FCB0,FIB0

8.50

0.10

#A1

Side View

Top View

63-Ball TBGA (measured in millimeters)

0.45

0.05

Bottom View

63-

∅

0.45

0.05

0.80 x 5= 4.00

0.80

0.10MAX

2.00

8.50

0.10

(Datum B)

(Datum A)

0.20

A B

∅

0.80 x 9= 7.20

15.00

0.10

#A1 INDEX MARK(OPTIONAL)

K9F1216U0A-YCB0,YIB0,PCB0,PIB0

FLASH MEMORY

K9F1216U0A-DCB0,DIB0,HCB0,HIB0

K9F1208U0A-YCB0,YIB0,PCB0,PIB0

K9F1208U0A-DCB0,DIB0,HCB0,HIB0

K9F1208Q0A-DCB0,DIB0,HCB0,HIB0

K9F1216Q0A-DCB0,DIB0,HCB0,HIB0

K9F1208U0A-VCB0,VIB0,FCB0,FIB0

PIN CONFIGURATION (WSOP1)

K9F1208U0A-VCB0,FCB0/VIB0,FIB0

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)

48 - WSOP1 - 1217F

Unit :mm

15.40

0.10

#24

-0

)

#48

#25

-0

0.58

0.04

0.70 MAX

(0.1Max)

17.00

0.20

0.45~0.75

N.C

DNU

N.C

R/B

DNU

N.C

Vcc

Vss

N.C

DNU

CLE

ALE

N.C

DNU

N.C

DNU

N.C

I/O7

I/O6

I/O5

I/O4

N.C

DNU

N.C

Vcc

Vss

N.C

DNU

N.C

I/O3

I/O2

I/O1

I/O0

N.C

DNU

N.C

K9F1216U0A-YCB0,YIB0,PCB0,PIB0

FLASH MEMORY

K9F1216U0A-DCB0,DIB0,HCB0,HIB0

K9F1208U0A-YCB0,YIB0,PCB0,PIB0

K9F1208U0A-DCB0,DIB0,HCB0,HIB0

K9F1208Q0A-DCB0,DIB0,HCB0,HIB0

K9F1216Q0A-DCB0,DIB0,HCB0,HIB0

K9F1208U0A-VCB0,VIB0,FCB0,FIB0

PIN DESCRIPTION

NOTE : Connect all V

and V

pins of each device to common power supply outputs.

Do not leave V

or V

disconnected.

Pin Name

Pin Function

I/O

~ I/O

(K9F1208X0A)

I/O

~ I/O

(K9F1216X0A)

DATA INPUTS/OUTPUTS

The I/O pins are used to input command, address and data, and to output data during read operations. The

I/O pins float to high-z when the chip is deselected or when the outputs are disabled.

I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-

ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and

output.

CLE

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high,

commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

ALE

ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are

latched on the rising edge of WE with ALE high.

CHIP ENABLE

The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and

the device does not return to standby mode in program or erase opertion. Regarding CE control during read

operation, refer to ’Page read’ section of Device operation .

READ ENABLE

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid

tREA after the falling edge of RE which also increments the internal column address counter by one.

WRITE ENABLE

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

the WE pulse.

WRITE PROTECT

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage

generator is reset when the WP pin is active low.

R/B

READY/BUSY OUTPUT

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or

random read operation is in process and returns to high state upon completion. It is an open drain output and

does not float to high-z condition when the chip is deselected or when outputs are disabled.

VccQ

OUTPUT BUFFER POWER

Q is the power supply for Output Buffer.

VccQ is internally connected to Vcc, thus should be biased to Vcc.

Vcc

POWER

is the power supply for device.

Vss

GROUND

N.C

NO CONNECTION

Lead is not internally connected.

DNU

DO NOT USE

Leave it disconnected.

K9F1216U0A-YCB0,YIB0,PCB0,PIB0

FLASH MEMORY

K9F1216U0A-DCB0,DIB0,HCB0,HIB0

K9F1208U0A-YCB0,YIB0,PCB0,PIB0

K9F1208U0A-DCB0,DIB0,HCB0,HIB0

K9F1208Q0A-DCB0,DIB0,HCB0,HIB0

K9F1216Q0A-DCB0,DIB0,HCB0,HIB0

K9F1208U0A-VCB0,VIB0,FCB0,FIB0

512Byte

16 Byte

Figure 1-1. K9F1208X0A (X8) FUNCTIONAL BLOCK DIAGRAM

Figure 2-1. K9F1208X0A (X8) ARRAY ORGANIZATION

X-Buffers

512M + 16M Bit

Command

NAND Flash

ARRAY

(512 + 16)Byte x 131072

Y-Gating

Page Register & S/A

I/O Buffers & Latches

Latches

& Decoders

Y-Buffers

Latches

& Decoders

Register

Control Logic

& High Voltage

Generator

Global Buffers

Output

Driver

- A

Command

I/0 0

I/0 7

CC/

CCQ

1st half Page Register

(=256 Bytes)

2nd half Page Register

(=256 Bytes)

128K Pages

(=4,096 Blocks)

512 Byte

8 bit

16 Byte

1 Block =32 Pages

= (16K + 512) Byte

I/O 0 ~ I/O 7

1 Page = 528 Byte

1 Block = 528 Byte x 32 Pages

= (16K + 512) Byte

1 Device = 528Bytes x 32Pages x 4096 Blocks

= 528 Mbits

Column Address

Row Address

(Page Address)

Page Register

CLE ALE

NOTE : Column Address : Starting Address of the Register.

00h Command(Read) : Defines the starting address of the 1st half of the register.

01h Command(Read) : Defines the starting address of the 2nd half of the register.

* A

is set to "Low" or "High" by the 00h or 01h Command.

* L must be set to "Low".

* The device ignores any additional input of address cycles than reguired.

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

1st Cycle