82C54

4-1

Semiconductor

March 1997

82C54

CMOS Programmable Interval Timer

Features

• 8MHz to 12MHz Clock Input Frequency

• Compatible with NMOS 8254

- Enhanced Version of NMOS 8253

• Three Independent 16-Bit Counters

• Six Programmable Counter Modes

• Status Read Back Command

• Binary or BCD Counting

• Fully TTL Compatible

• Single 5V Power Supply

• Low Power

- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA at 8MHz

• Operating Temperature Ranges

- C82C54 . . . . . . . . . . . . . . . . . . . . . . . . . .0

C to +70

- I82C54 . . . . . . . . . . . . . . . . . . . . . . . . . -40

C to +85

- M82C54 . . . . . . . . . . . . . . . . . . . . . . . -55

C to +125

Description

The Harris 82C54 is a high performance CMOS Programma-

ble Interval Timer manufactured using an advanced 2 micron

CMOS process.

The 82C54 has three independently programmable and

functional 16-bit counters, each capable of handling clock

input frequencies of up to 8MHz (82C54) or 10MHz

(82C54-10) or 12MHz (82C54-12).

The high speed and industry standard conﬁguration of the

82C54 make it compatible with the Harris 80C86, 80C88,

and 80C286 CMOS microprocessors along with many other

industry standard processors. Six programmable timer

modes allow the 82C54 to be used as an event counter,

elapsed time indicator, programmable one-shot, and many

other applications. Static CMOS circuit design insures low

power operation.

The Harris advanced CMOS process results in a signiﬁcant

reduction in power with performance equal to or greater than

existing equivalent products.

Pinouts

82C54 (PDIP, CERDIP, SOIC)

TOP VIEW

82C54 (PLCC/CLCC)

TOP VIEW

CLK 0

OUT 0

GATE 0

GND

VCC

OUT 2

CLK 1

GATE 1

OUT 1

CLK 2

GATE 2

GND

OUT 1

TE 1

CLK 1

OUT 0

TE 0

VCC

CLK2

GATE 2

OUT 2

CLK 0

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Harris Corporation 1997

File Number

2970.1

4-2

Functional Diagram

Ordering Information

PART NUMBERS

TEMPERATURE

RANGE

PACKAGE

PKG. NO.

8MHz

10MHz

12MHz

CP82C54

CP82C54-10

CP82C54-12

C to +70

24 Lead PDIP

E24.6

IP82C54

IP82C54-10

IP82C54-12

-40

C to +85

24 Lead PDIP

E24.6

CS82C54

CS82C54-10

CS82C54-12

C to +70

28 Lead PLCC

N28.45

IS82C54

IS82C54-10

IS82C54-12

-40

C to +85

28 Lead PLCC

N28.45

CD82C54

CD82C54-10

CD82C54-12

C to +70

24 Lead CERDIP

F24.6

ID82C54

ID82C54-10

ID82C54-12

-40

C to +85

24 Lead CERDIP

F24.6

MD82C54/B

MD82C54-10/B

MD82C54-12/B

-55

C to +125

24 Lead CERDIP

F24.6

MR82C54/B

MR82C54-10/B

MR82C54-12/B

-55

C to +125

28 Lead CLCC

J28.A

SMD # 8406501JA

8406502JA

-55

C to +125

24 Lead CERDIP

F24.6

SMD# 84065013A

84065023A

-55

C to +125

28 Lead CLCC

J28.A

CM82C54

CM82C54-10

CM82C54-12

C to +70

24 Lead SOIC

M24.3

Pin Description

SYMBOL

DIP PIN

NUMBER

TYPE

DEFINITION

D7 - D0

1 - 8

I/O

DATA: Bi-directional three-state data bus lines, connected to system data bus.

CLK 0

CLOCK 0: Clock input of Counter 0.

OUT 0

OUT 0: Output of Counter 0.

GATE 0

GATE 0: Gate input of Counter 0.

GND

GROUND: Power supply connection.

OUT 1

OUT 1: Output of Counter 1.

GATE 1

GATE 1: Gate input of Counter 1.

CLK 1

CLOCK 1: Clock input of Counter 1.

GATE 2

GATE 2: Gate input of Counter 2.

OUT 2

OUT 2: Output of Counter 2.

CONTROL

WORD

REGISTER

READ/

WRITE

LOGIC

DATA/

BUS

BUFFER

COUNTER

INTERNAL B

INTERNAL BUS

CONTROL

LOGIC

CONTROL

WORD

REGISTER

STATUS

LATCH

STATUS

REGISTER

CLK n

GATE n

OUT n

OUT 2

GATE 2

CLK 2

OUT 1

GATE 1

CLK 1

OUT 0

GATE 0

CLK 0

- D

COUNTER INTERNAL BLOCK DIAGRAM

82C54

4-3

Functional Description

General

The 82C54 is a programmable interval timer/counter

designed for use with microcomputer systems. It is a general

purpose, multi-timing element that can be treated as an

array of I/O ports in the system software.

The 82C54 solves one of the most common problems in any

microcomputer system, the generation of accurate time

delays under software control. Instead of setting up timing

loops in software, the programmer conﬁgures the 82C54 to

match his requirements and programs one of the counters

for the desired delay. After the desired delay, the 82C54 will

interrupt the CPU. Software overhead is minimal and vari-

able length delays can easily be accommodated.

Some of the other computer/timer functions common to micro-

computers which can be implemented with the 82C54 are:

• Real time clock

• Event counter

• Digital one-shot

• Programmable rate generator

• Square wave generator

• Binary rate multiplier

• Complex waveform generator

• Complex motor controller

Data Bus Buffer

This three-state, bi-directional, 8-bit buffer is used to inter-

face the 82C54 to the system bus (see Figure 1).

Read/Write Logic

The Read/Write Logic accepts inputs from the system bus and

generates control signals for the other functional blocks of the

82C54. A1 and A0 select one of the three counters or the Con-

trol Word Register to be read from/written into. A “low” on the

RD input tells the 82C54 that the CPU is reading one of the

counters. A “low” on the WR input tells the 82C54 that the CPU

is writing either a Control Word or an initial count. Both RD and

WR are qualiﬁed by CS; RD and WR are ignored unless the

82C54 has been selected by holding CS low.

CLK 2

CLOCK 2: Clock input of Counter 2.

A0, A1

19 - 20

ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write

operations. Normally connected to the system address bus.

CHIP SELECT: A low on this input enables the 82C54 to respond to RD and WR signals. RD and

WR are ignored otherwise.

READ: This input is low during CPU read operations.

WRITE: This input is low during CPU write operations.

: The +5V power supply pin. A 0.1

F capacitor between pins VCC and GND is recommended

for decoupling.

Pin Description

(Continued)

SYMBOL

DIP PIN

NUMBER

TYPE

DEFINITION

SELECTS

Counter 0

Counter 1

Counter 2

Control Word Register

CONTROL

WORD

REGISTER

COUNTER

INTERNAL B

OUT 2

GATE 2

CLK 2

OUT 1

GATE 1

CLK 1

OUT 0

GATE 0

CLK 0

- D

FIGURE 1. DATA BUS BUFFER AND READ/WRITE LOGIC

FUNCTIONS

DATA/

BUS

BUFFER

READ/

WRITE

LOGIC

82C54

4-4

Control Word Register

The Control Word Register (Figure 2) is selected by the

Read/Write Logic when A1, A0 = 11. If the CPU then does a

write operation to the 82C54, the data is stored in the Con-

trol Word Register and is interpreted as a Control Word used

to deﬁne the Counter operation.

The Control Word Register can only be written to; status

information is available with the Read-Back Command.

Counter 0, Counter 1, Counter 2

These three functional blocks are identical in operation, so

only a single Counter will be described. The internal block

diagram of a signal counter is shown in Figure 3. The

counters are fully independent. Each Counter may operate

in a different Mode.

The Control Word Register is shown in the ﬁgure; it is not

part of the Counter itself, but its contents determine how the

Counter operates.

The status register, shown in the ﬁgure, when latched, con-

tains the current contents of the Control Word Register and

status of the output and null count ﬂag. (See detailed expla-

nation of the Read-Back command.)

The actual counter is labeled CE (for Counting Element). It is

a 16-bit presettable synchronous down counter.

OLM and OLL are two 8-bit latches. OL stands for “Output

Latch”; the subscripts M and L for “Most signiﬁcant byte” and

“Least signiﬁcant byte”, respectively. Both are normally referred

to as one unit and called just OL. These latches normally “fol-

low” the CE, but if a suitable Counter Latch Command is sent to

the 82C54, the latches “latch” the present count until read by

the CPU and then return to “following” the CE. One latch at a

time is enabled by the counter’s Control Logic to drive the inter-

nal bus. This is how the 16-bit Counter communicates over the

8-bit internal bus. Note that the CE itself cannot be read; when-

ever you read the count, it is the OL that is being read.

Similarly, there are two 8-bit registers called CRM and CRL (for

“Count Register”). Both are normally referred to as one unit and

called just CR. When a new count is written to the Counter, the

count is stored in the CR and later transferred to the CE. The

Control Logic allows one register at a time to be loaded from

the internal bus. Both bytes are transferred to the CE simulta-

neously. CRM and CRL are cleared when the Counter is pro-

grammed for one byte counts (either most signiﬁcant byte only

or least signiﬁcant byte only) the other byte will be zero. Note

that the CE cannot be written into; whenever a count is written,

it is written into the CR.

The Control Logic is also shown in the diagram. CLK n,

GATE n, and OUT n are all connected to the outside world

through the Control Logic.

82C54 System Interface

The 82C54 is treated by the system software as an array of

peripheral I/O ports; three are counters and the fourth is a

control register for MODE programming.

Basically, the select inputs A0, A1 connect to the A0, A1

address bus signals of the CPU. The CS can be derived

directly from the address bus using a linear select method or

it can be connected to the output of a decoder.

READ/

WRITE

LOGIC

DATA/

BUS

BUFFER

INTERNAL B

OUT 2

GATE 2

CLK 2

OUT 1

GATE 1

CLK 1

OUT 0

GATE 0

CLK 0

- D

FIGURE 2. CONTROL WORD REGISTER AND COUNTER

FUNCTIONS

CONTROL

WORD

REGISTER

COUNTER

INTERNAL BUS

CONTROL

LOGIC

CONTROL

WORD

REGISTER

STATUS

LATCH

STATUS

REGISTER

CLK n

GATE n

OUT n

FIGURE 3. COUNTER INTERNAL BLOCK DIAGRAM

82C54

4-5

Operational Description

General

After power-up, the state of the 82C54 is undeﬁned. The

Mode, count value, and output of all Counters are undeﬁned.

How each Counter operates is determined when it is pro-

grammed. Each Counter must be programmed before it can

be used. Unused counters need not be programmed.

Programming the 82C54

Counters are programmed by writing a Control Word and

then an initial count.

All Control Words are written into the Control Word Register,

which is selected when A1, A0 = 11. The Control Word spec-

iﬁes which Counter is being programmed.

By contrast, initial counts are written into the Counters, not

the Control Word Register. The A1, A0 inputs are used to

select the Counter to be written into. The format of the initial

count is determined by the Control Word used.

FIGURE 4. 82C54 SYSTEM INTERFACE

Write Operations

The programming procedure for the 82C54 is very ﬂexible.

Only two conventions need to be remembered:

1. For Each Counter, the Control Word must be written

before the initial count is written.

2. The initial count must follow the count format speciﬁed in the

Control Word (least signiﬁcant byte only, most signiﬁcant byte

only, or least signiﬁcant byte and then most signiﬁcant byte).

Since the Control Word Register and the three Counters have

separate addresses (selected by the A1, A0 inputs), and each

Control Word speciﬁes the Counter it applies to (SC0, SC1 bits),

no special instruction sequence is required. Any programming

sequence that follows the conventions above is acceptable.

Control Word Format

A1, A0 = 11; CS = 0; RD = 1; WR = 0

SC1

SC0

RW1

RW0

BCD

ADDRESS BUS (16)

CONTROL BUS

DATA BUS (8)

I/OR I/OW

COUNTER

OUT GATE CLK

COUNTER

OUT GATE CLK

D0 - D7

82C54

SC - Select Counter

SC1

SC0

Select Counter 0

Select Counter 1

Select Counter 2

Read-Back Command (See Read Operations)

RW - Read/Write

RW1 RW0

Counter Latch Command (See Read Operations)

Read/Write least significant byte only.

Read/Write most significant byte only.

Read/Write least significant byte first, then most

significant byte.

M - Mode

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

BCD - Binary Coded Decimal

Binary Counter 16-bit

Binary Coded Decimal (BCD) Counter (4 Decades)

NOTE: Don’t Care bits (X) should be 0 to insure compatibility with

future products.

Possible Programming Sequence

Control Word - Counter 0

LSB of Count - Counter 0

MSB of Count - Counter 0

Control Word - Counter 1

LSB of Count - Counter 1

MSB of Count - Counter 1

Control Word - Counter 2

LSB of Count - Counter 2

MSB of Count - Counter 2

Possible Programming Sequence

Control Word - Counter 0

Control Word - Counter 1

Control Word - Counter 2

LSB of Count - Counter 2

82C54

4-6

A new initial count may be written to a Counter at any time

without affecting the Counter’s programmed Mode in any way.

Counting will be affected as described in the Mode deﬁnitions.

The new count must follow the programmed count format.

If a Counter is programmed to read/write two-byte counts,

the following precaution applies. A program must not transfer

control between writing the ﬁrst and second byte to another

routine which also writes into that same Counter. Otherwise,

the Counter will be loaded with an incorrect count.

Read Operations

It is often desirable to read the value of a Counter without

disturbing the count in progress. This is easily done in the

82C54.

There are three possible methods for reading the Counters.

The ﬁrst is through the Read-Back command, which is

explained later. The second is a simple read operation of the

Counter, which is selected with the A1, A0 inputs. The only

requirement is that the CLK input of the selected Counter

must be inhibited by using either the GATE input or external

logic. Otherwise, the count may be in process of changing

when it is read, giving an undeﬁned result.

Counter Latch Command

The other method for reading the Counters involves a spe-

cial software command called the “Counter Latch Com-

mand”. Like a Control Word, this command is written to the

Control Word Register, which is selected when A1, A0 = 11.

Also, like a Control Word, the SC0, SC1 bits select one of

the three Counters, but two other bits, D5 and D4, distin-

guish this command from a Control Word.

The selected Counter’s output latch (OL) latches the count

when the Counter Latch Command is received. This count is

held in the latch until it is read by the CPU (or until the Counter

is reprogrammed). The count is then unlatched automatically

and the OL returns to “following” the counting element (CE).

This allows reading the contents of the Counters “on the ﬂy”

without affecting counting in progress. Multiple Counter Latch

Commands may be used to latch more than one Counter.

Each latched Counter’s OL holds its count until read. Counter

Latch Commands do not affect the programmed Mode of the

Counter in any way.

If a Counter is latched and then, some time later, latched

again before the count is read, the second Counter Latch

Command is ignored. The count read will be the count at the

time the ﬁrst Counter Latch Command was issued.

With either method, the count must be read according to the

programmed format; speciﬁcally, if the Counter is pro-

grammed for two byte counts, two bytes must be read. The

two bytes do not have to be read one right after the other;

read or write or programming operations of other Counters

may be inserted between them.

Another feature of the 82C54 is that reads and writes of the

same Counter may be interleaved; for example, if the

Counter is programmed for two byte counts, the following

sequence is valid.

LSB of Count - Counter 1

LSB of Count - Counter 0

MSB of Count - Counter 0

MSB of Count - Counter 1

MSB of Count - Counter 2

Possible Programming Sequence

Control Word - Counter 2

Control Word - Counter 1

Control Word - Counter 0

LSB of Count - Counter 2

MSB of Count - Counter 2

LSB of Count - Counter 1

MSB of Count - Counter 1

LSB of Count - Counter 0

MSB of Count - Counter 0

Possible Programming Sequence

Control Word - Counter 1

Control Word - Counter 0

LSB of Count - Counter 1

Control Word - Counter 2

LSB of Count - Counter 0

MSB of Count - Counter 1

LSB of Count - Counter 2

MSB of Count - Counter 0

MSB of Count - Counter 2

NOTE: In all four examples, all counters are programmed to

Read/Write two-byte counts. These are only four of many

programming sequences.

Possible Programming Sequence

(Continued)

A1, A0 = 11; CS = 0; RD = 1; WR = 0

SC1

SC0

SC1, SC0 - specify counter to be latched

SC1

SC0

COUNTER

Read-Back Command

D5, D4 - 00 designates Counter Latch Command, X - Don’t Care.

NOTE: Don’t Care bits (X) should be 0 to insure compatibility with

future products.

82C54

4-7

1. Read least signiﬁcant byte.

2. Write new least signiﬁcant byte.

3. Read most signiﬁcant byte.

4. Write new most signiﬁcant byte.

If a counter is programmed to read or write two-byte counts,

the following precaution applies: A program MUST NOT

transfer control between reading the ﬁrst and second byte to

another routine which also reads from that same Counter.

Otherwise, an incorrect count will be read.

Read-Back Command

The read-back command allows the user to check the count

value, programmed Mode, and current state of the OUT pin

and Null Count ﬂag of the selected counter(s).

The command is written into the Control Word Register and

has the format shown in Figure 5. The command applies to

the counters selected by setting their corresponding bits D3,

D2, D1 = 1.

The read-back command may be used to latch multiple

counter output latches (OL) by setting the COUNT bit D5 = 0

and selecting the desired counter(s). This signal command

is functionally equivalent to several counter latch commands,

one for each counter latched. Each counter’s latched count

is held until it is read (or the counter is reprogrammed). That

counter is automatically unlatched when read, but other

counters remain latched until they are read. If multiple count

read-back commands are issued to the same counter with-

out reading the count, all but the ﬁrst are ignored; i.e., the

count which will be read is the count at the time the ﬁrst

read-back command was issued.

The read-back command may also be used to latch status

information of selected counter(s) by setting STATUS bit D4

= 0. Status must be latched to be read; status of a counter is

accessed by a read from that counter.

The counter status format is shown in Figure 6. Bits D5

through D0 contain the counter’s programmed Mode exactly

as written in the last Mode Control Word. OUTPUT bit D7

contains the current state of the OUT pin. This allows the

user to monitor the counter’s output via software, possibly

eliminating some hardware from a system.

NULL COUNT bit D6 indicates when the last count written to

the counter register (CR) has been loaded into the counting

element (CE). The exact time this happens depends on the

Mode of the counter and is described in the Mode Deﬁnitions,

but until the counter is loaded into the counting element (CE),

it can’t be read from the counter. If the count is latched or read

before this time, the count value will not reﬂect the new count

just written. The operation of Null Count is shown below.

THIS ACTION:

CAUSES:

A. Write to the control word register:(1) . . . . . . . . . . Null Count = 1

B. Write to the count register (CR):(2) . . . . . . . . . . . Null Count = 1

C. New count is loaded into CE (CR - CE) . . . . . . . . Null Count = 0

(1) Only the counter speciﬁed by the control word will have its null

count set to 1. Null count bits of other counters are unaffected.

(2) If the counter is programmed for two-byte counts (least signiﬁ-

cant byte then most signiﬁcant byte) null count goes to 1 when

the second byte is written.

If multiple status latch operations of the counter(s) are per-

formed without reading the status, all but the ﬁrst are ignored;

i.e., the status that will be read is the status of the counter at

the time the ﬁrst status read-back command was issued.

FIGURE 7. READ-BACK COMMAND EXAMPLE

A0, A1 = 11; CS = 0; RD = 1; WR = 0

COUNT

STATUS

CNT 2 CNT 1 CNT 0

D5: 0 = Latch count of selected Counter (s)

D4: 0 = Latch status of selected Counter(s)

D3: 1 = Select Counter 2

D2: 1 = Select Counter 1

D1: 1 = Select Counter 0

D0: Reserved for future expansion; Must be 0

FIGURE 5. READ-BACK COMMAND FORMAT

OUTPUT

NULL

COUNT

RW1 RW0

BCD

D7: 1

= Out pin is 1

= Out pin is 0

D6: 1

= Null count