54ACTQ16240
16-Bit Inverting Buffer/Line Driver with TRI-STATE
®
Outputs
General Description
The ’ACTQ16240 contains sixteen inverting buffers with
TRI-STATE outputs designed to be employed as a memory
and address driver, clock driver, or bus-oriented transmitter/
receiver. The device is nibble controlled. Each nibble has
separate TRI-STATE control inputs which can be shorted to-
gether for full 16-bit operation.
The ’ACTQ16240 utilizes NSC Quiet Series technology to
guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series
™
features
GTO
™
output control for superior performance.
Features
n
Utilizes NSC FACT Quiet Series technology
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Separate control logic for each byte
n
16-bit version of the ’ACTQ240
n
Outputs source/sink 24 mA
n
Standard Microcircuit Drawing (SMD) 5962-9688001
Logic Symbol
Pin Description
Pin
Description
Names
OE
n
Output Enable Inputs (Active Low)
I
0
–I
15
Inputs
O
0
–O
15
Outputs
Connection Diagram
FACT
®
is a trademark of National Semiconductor Corporation.
FACT Quiet Series
®
is a trademark of National Semiconductor Corporation.
GTO
®
is a trademark of National Semiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
DS010924-1
Pin Assignment for CERPAK
DS010924-2
September 1998
54ACTQ16240
16-Bit
Inverting
Buffer/Line
Driver
with
TRI-ST
A
T
E
Outputs
© 1998 National Semiconductor Corporation
DS010924
www.national.com
Functional Description
The ’ACTQ16240 contains sixteen inverting buffers with
TRI-STATE standard outputs. The device is nibble (4 bits)
controlled with each nibble functioning identically, but inde-
pendent of the other. The control pins may be shorted to-
gether to obtain full 16-bit operation. The TRI-STATE outputs
are controlled by an Output Enable (OE
n
) input for each
nibble. When OE
n
is LOW, the outputs are in 2-state mode.
When OE
n
is HIGH, the outputs are in the high impedance
mode, but this does not interfere with entering new data into
the inputs.
Logic Diagram
Truth Tables
Inputs
Outputs
OE
1
I
0
–I
3
O
0
–O
3
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
OE
2
I
4
–I
7
O
4
–O
7
L
L
H
L
H
L
H
X
Z
H = High Voltage Level
L = Low Voltage Level
X = Immaterial
Z = High Impedance
Inputs
Outputs
OE
3
I
8
–I
11
O
8
–O
11
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
OE
4
I
12
–I
15
O
12
–O
15
L
L
H
L
H
L
H
X
Z
DS010924-3
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
−0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V
−20 mA
V
I
= V
CC
+ 0.5V
+20 mA
DC Output Diode Current (I
OK
)
V
O
= −0.5V
−20 mA
V
O
= V
CC
+ 0.5V
+20 mA
DC Output Voltage (V
O
)
−0.5V to V
CC
+ 0.5V
DC Output Source/Sink Current (I
O
)
±
50 mA
DC V
CC
or Ground Current
per Output Pin
±
50 mA
Junction Temperature
CDIP
+175˚C
Storage Temperature
−65˚C to +150˚C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
’ACTQ
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
54ACTQ
−55˚C to +125˚C
Minimum Input Edge Rate (dV/dt)
’ACTQ Devices
125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
™
circuits outside databook specifications.
DC Electrical Characteristics for ’ACTQ Family Devices
Symbol
Parameter
V
CC
(V)
54ACTQ
Units
Conditions
T
A
=
−55˚C to +125˚C
Guaranteed Limits
V
IH
Minimum High
4.5
2.0
V
V
OUT
= 0.1V
Input Voltage
5.5
2.0
or V
CC
− 0.1V
V
IL
Maximum Low
4.5
0.8
V
V
OUT
= 0.1V
Input Voltage
5.5
0.8
or V
CC
− 0.1V
V
OH
Minimum High
4.5
4.4
V
I
OUT
= −50 µA
Output Voltage
5.5
5.4
(Note 2)
V
IN
= V
IL
or V
IH
4.5
3.70
V
I
OH
= −24 mA
5.5
4.70
I
OH
= −24 mA
V
OL
Maximum Low
4.5
0.1
V
I
OUT
= 50 µA
Output Voltage
5.5
0.1
(Note 2)
V
IN
= V
IL
or V
IH
4.5
0.50
V
I
OL
= 24 mA
5.5
0.50
I
OL
= 24 mA
I
OZ
Maximum TRI-STATE
5.5
±
10.0
µA
V
I
= V
IL
, V
IH
Leakage Current
V
O
= V
CC
, GND
I
IN
Maximum Input
5.5
±
1.0
µA
V
I
= V
CC
, GND
Leakage Current
I
CCT
Maximum I
CC
/Input
5.5
1.6
mA
V
I
= V
CC
− 2.1V
I
CC
Max Quiescent
5.5
160.0
µA
V
IN
= V
CC
Supply Current
or GND
(Note 6)
I
OLD
Minimum Dynamic
Output Current
(Note 3)
5.5
50
mA
V
OLD
= 1.65V Max
I
OHD
50
mA
V
OHD
= 3.85V Min
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3
DC Electrical Characteristics for ’ACTQ Family Devices
(Continued)
Symbol
Parameter
V
CC
(V)
54ACTQ
Units
Conditions
T
A
=
−55˚C to +125˚C
Guaranteed Limits
V
OLP
Quiet Output
5.0
1.2
V
Maximum Dynamic
V
OL
(Notes 4, 5)
V
OLV
Quiet Output
5.0
-1.2
V
Minimum Dynamic
V
OL
(Notes 4, 5)
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
Note 4: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched LOW and one output held LOW.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched HIGH and one output held HIGH.
Note 6: I
CC
for 54ACTQ
@
25˚C is identical to 74ACTQ
@
25˚C.
AC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
(Note 7)
54ACTQ
Units
T
A
=
−55˚C to +125˚C
C
L
= 50 pF
Min
Max
t
PLH
,
Propagation Delay
5.0
2.5
9.0
ns
t
PHL
Data to Output
2.5
8.0
t
PZH
,
Output Enable Time
5.0
2.5
8.5
ns
t
PZL
2.5
8.9
t
PHZ
,
Output Disable Time
5.0
2.0
8.3
ns
t
PLZ
2.0
8.3
Note 7: Voltage Range 5.0 is 5.0V
±
0.5V.
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Pin Capacitance
4.5
pF
V
CC
= 5.0V
C
PD
Power Dissipation
Capacitance
95
pF
V
CC
= 5.0V
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4
5
Physical Dimensions
inches (millimeters) unless otherwise noted
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the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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48-Lead CERPAK (F)
NS Package Number WA48A
54ACTQ16240
16-Bit
Inverting
Buffer/Line
Driver
with
TRI-ST
A
T
E
Outputs
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.