Document:

Philips Semiconductors

Product specification

80C51/87C51/80C52/87C52

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),

low power, high speed (33 MHz), 128/256 B RAM

2000 Aug 07

853–0169 24291

DESCRIPTION

The Philips 80C51/87C51/80C52/87C52 is a high-performance

static 80C51 design fabricated with Philips high-density CMOS

technology with operation from 2.7 V to 5.5 V.

The 8xC51 and 8xC52 contain a 128

8 RAM and 256

8 RAM

respectively, 32 I/O lines, three 16-bit counter/timers, a six-source,

four-priority level nested interrupt structure, a serial I/O port for

either multi-processor communications, I/O expansion or full duplex

UART, and on-chip oscillator and clock circuits.

In addition, the device is a low power static design which offers a

wide range of operating frequencies down to zero. Two software

selectable modes of power reduction—idle mode and power-down

mode are available. The idle mode freezes the CPU while allowing

the RAM, timers, serial port, and interrupt system to continue

functioning. The power-down mode saves the RAM contents but

freezes the oscillator, causing all other chip functions to be

inoperative. Since the design is static, the clock can be stopped

without loss of user data and then the execution resumed from the

point the clock was stopped.

SELECTION TABLE

For applications requiring more ROM and RAM, see the 8XC54/58

and 8XC51RA+/RB+/RC+/80C51RA+ data sheet.

Note: 80C31/80C32 is specified in separate data sheet.

ROM/EPROM

Memory Size

(X by 8)

RAM Size

(X by 8)

Programmable

Timer Counter

(PCA)

Hardware

Watch Dog

Timer

80C31*/80C51/87C51

0K/4K

128

80C32*/80C52/87C52

0K/8K/16K/32K

256

80C51RA+/8XC51RA+/RB+/RC+

0K/8K/16K/32K

512

Yes

8XC51RD+

64K

1024

Yes

FEATURES

•

8051 Central Processing Unit

– 4k

8 ROM (80C51)

– 8k

8 ROM (80C52)

– 128

8 RAM (80C51)

– 256

8 RAM (80C52)

– Three 16-bit counter/timers

– Boolean processor

– Full static operation

– Low voltage (2.7 V to 5.5 V@ 16 MHz) operation

•

Memory addressing capability

– 64k ROM and 64k RAM

•

Power control modes:

– Clock can be stopped and resumed

– Idle mode

– Power-down mode

•

CMOS and TTL compatible

•

TWO speed ranges at V

= 5 V

– 0 to 16 MHz

– 0 to 33 MHz

•

Three package styles

•

Extended temperature ranges

•

Dual Data Pointers

•

Security bits:

– ROM (2 bits)

– OTP/EPROM (3 bits)

•

Encryption array – 64 bytes

•

4 level priority interrupt

•

6 interrupt sources

•

Four 8-bit I/O ports

•

Full–duplex enhanced UART

– Framing error detection

– Automatic address recognition

•

Programmable clock out

•

Asynchronous port reset

•

Low EMI (inhibit ALE and slew rate controlled outputs)

•

Wake-up from Power Down by an external interrupt

Philips Semiconductors

Product specification

80C51/87C51/80C52/87C52

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),

low power, high speed (33 MHz), 128/256 B RAM

2000 Aug 07

80C51/87C51 ORDERING INFORMATION

MEMORY SIZE

TEMPERATURE RANGE

AND PACKAGE

VOLTAGE

RANGE

FREQ.

(MHz)

DWG. #

ROM

P80C51SBPN

0 to +70 Plastic Dual In line Package

2 7 V to 5 5 V

0 to 16

SOT129 1

OTP

P87C51SBPN

0 to +70, Plastic Dual In-line Package

2.7 V to 5.5 V

0 to 16

SOT129-1

ROM

P80C51SBAA

0 to +70 Plastic Leaded Chip Carrier

2 7 V to 5 5 V

0 to 16

SOT187 2

OTP

P87C51SBAA

0 to +70, Plastic Leaded Chip Carrier

2.7 V to 5.5 V

0 to 16

SOT187-2

ROM

P80C51SBBB

0 to +70 Plastic Quad Flat Pack

2 7 V to 5 5 V

0 to 16

SOT307 2

OTP

P87C51SBBB

0 to +70, Plastic Quad Flat Pack

2.7 V to 5.5 V

0 to 16

SOT307-2

ROM

P80C51SFP N

40 to +85 Plastic Dual In line Package

2 7 V to 5 5 V

0 to 16

SOT129 1

OTP

P87C51SFP N

–40 to +85, Plastic Dual In-line Package

2.7 V to 5.5 V

0 to 16

SOT129-1

ROM

P80C51SFA A

40 to +85 Plastic Leaded Chip Carrier

2 7 V to 5 5 V

0 to 16

SOT187 2

OTP

P87C51SFA A

–40 to +85, Plastic Leaded Chip Carrier

2.7 V to 5.5 V

0 to 16

SOT187-2

ROM

P80C51SFB B

40 to +85 Plastic Quad Flat Pack

2 7 V to 5 5 V

0 to 16

SOT307 2

OTP

P87C51SFB B

–40 to +85, Plastic Quad Flat Pack

2.7 V to 5.5 V

0 to 16

SOT307-2

ROM

P80C51UBAA

0 to +70 Plastic Leaded Chip Carrier

5 V

0 to 33

SOT187 2

OTP

P87C51UBAA

0 to +70, Plastic Leaded Chip Carrier

5 V

0 to 33

SOT187-2

ROM

P80C51UBPN

0 to +70 Plastic Dual In line Package

5 V

0 to 33

SOT129 1

OTP

P87C51UBPN

0 to +70, Plastic Dual In-line Package

5 V

0 to 33

SOT129-1

ROM

P80C51UFA A

40 to +85 Plastic Leaded Chip Carrier

5 V

0 to 33

SOT187 2

OTP

P87C51UFA A

–40 to +85, Plastic Leaded Chip Carrier

5 V

0 to 33

SOT187-2

PART NUMBER DERIVATION

DEVICE

NUMBER

DEVICE

NUMBER

OPERATING FREQUENCY, MAX (S)

TEMPERATURE RANGE (B)

PACKAGE (AA)

ROM

P80C51

S = 16 MHz

B = 0

to +70

AA = PLCC

ROM

P80C52

S = 16 MHz

B = 0

to +70

AA = PLCC

OTP

P87C51

U = 33 MHz

F = –40

C to +85

BB = PQFP

OTP

P87C52

U = 33 MHz

F = –40

C to +85

BB = PQFP

Philips Semiconductors

Product specification

80C51/87C51/80C52/87C52

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),

low power, high speed (33 MHz), 128/256 B RAM

2000 Aug 07

80C52/87C52 ORDERING INFORMATION

MEMORY SIZE

TEMPERATURE RANGE

AND PACKAGE

VOLTAGE

RANGE

FREQ.

(MHz)

DWG. #

ROM

P80C52SBPN

0 to +70 Plastic Dual In line Package

2 7 V to 5 5 V

0 to 16

SOT129 1

OTP

P87C52SBPN

0 to +70, Plastic Dual In-line Package

2.7 V to 5.5 V

0 to 16

SOT129-1

ROM

P80C52SBAA

0 to +70 Plastic Leaded Chip Carrier

2 7 V to 5 5 V

0 to 16

SOT187 2

OTP

P87C52SBAA

0 to +70, Plastic Leaded Chip Carrier

2.7 V to 5.5 V

0 to 16

SOT187-2

ROM

P80C52SBBB

0 to +70 Plastic Quad Flat Pack

2 7 V to 5 5 V

0 to 16

SOT307 2

OTP

P87C52SBBB

0 to +70, Plastic Quad Flat Pack

2.7 V to 5.5 V

0 to 16

SOT307-2

ROM

P80C52SFP N

40 to +85 Plastic Dual In line Package

2 7 V to 5 5 V

0 to 16

SOT129 1

OTP

P87C52SFP N

–40 to +85, Plastic Dual In-line Package

2.7 V to 5.5 V

0 to 16

SOT129-1

ROM

P80C52SFA A

40 to +85 Plastic Leaded Chip Carrier

2 7 V to 5 5 V

0 to 16

SOT187 2

OTP

P87C52SFA A

–40 to +85, Plastic Leaded Chip Carrier

2.7 V to 5.5 V

0 to 16

SOT187-2

ROM

P80C52SFB B

40 to +85 Plastic Quad Flat Pack

2 7 V to 5 5 V

0 to 16

SOT307 2

OTP

P87C52SFB B

–40 to +85, Plastic Quad Flat Pack

2.7 V to 5.5 V

0 to 16

SOT307-2

ROM

P80C52UBAA

0 to +70 Plastic Leaded Chip Carrier

5 V

0 to 33

SOT187 2

OTP

P87C52UBAA

0 to +70, Plastic Leaded Chip Carrier

5 V

0 to 33

SOT187-2

ROM

P80C52UBPN

0 to +70 Plastic Dual In line Package

5 V

0 to 33

SOT129 1

OTP

P87C52UBPN

0 to +70, Plastic Dual In-line Package

5 V

0 to 33

SOT129-1

ROM

P80C52UFA A

40 to +85 Plastic Leaded Chip Carrier

5 V

0 to 33

SOT187 2

OTP

P87C52UFA A

–40 to +85, Plastic Leaded Chip Carrier

5 V

0 to 33

SOT187-2

Philips Semiconductors

Product specification

80C51/87C51/80C52/87C52

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),

low power, high speed (33 MHz), 128/256 B RAM

2000 Aug 07

LOGIC SYMBOL

POR

ADDRESS AND

DATA BUS

ADDRESS BUS

T2EX

RxD

TxD

INT0

INT1

SECONDAR

FUNCTIONS

RST

EA/V

PSEN

ALE/PROG

XTAL1

XTAL2

SU00830

PIN CONFIGURATIONS

SU01063

T2/P1.0

T2EX/P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

RST

RxD/P3.0

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

P1.7

WR/P3.6

RD/P3.7

XTAL2

XTAL1

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE

EA/V

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

DUAL

IN-LINE

PACKAGE

PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS

SU01062

LCC

Pin

Function

NIC*

P1.0/T2

P1.1/T2EX

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

P3.0/RxD

NIC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

Pin

Function

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

NIC*

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

Pin

Function

P2.7/A15

PSEN

ALE

NIC*

EA/V

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

* NO INTERNAL CONNECTION

PLASTIC QUAD FLAT PACK

PIN FUNCTIONS

SU01064

PQFP

Pin

Function

P1.5

P1.6

P1.7

RST

P3.0/RxD

NIC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

Pin

Function

NIC*

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE

NIC*

EA/V

P0.7/AD7

Pin

Function

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

NIC*

P1.0/T2

P1.1/T2EX

P1.2

P1.3

P1.4

* NO INTERNAL CONNECTION

Philips Semiconductors

Product specification

80C51/87C51/80C52/87C52

80C51 8-bit microcontroller family

4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),

low power, high speed (33 MHz), 128/256 B RAM

2000 Aug 07

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC

DIP

LCC

QFP

TYPE

NAME AND FUNCTION

Ground: 0 V reference.

Power Supply: This is the power supply voltage for normal, idle, and power-down operation.

P0.0–0.7

39–32

43–36

37–30

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port with Schmitt trigger inputs. Port 0 pins

that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also

the multiplexed low-order address and data bus during accesses to external program and

data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0

also outputs the code bytes during program verification and received code bytes during

EPROM programming. External pull-ups are required during program verification.

P1.0–P1.7

1–8

2–9

40–44,

1–3

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger

inputs. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and

can be used as inputs. As inputs, port 1 pins that are externally pulled low will source

current because of the internal pull-ups. (See DC Electrical Characteristics: I

). Port 1 also

receives the low-order address byte during program memory verification. Alternate functions

for Port 1 include:

I/O

T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable Clock-Out)

T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control

P2.0–P2.7

21–28

24–31

18–25

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger

inputs. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and

can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source

current because of the internal pull-ups. (See DC Electrical Characteristics: I

). Port 2 emits

the high-order address byte during fetches from external program memory and during

accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this

application, it uses strong internal pull-ups when emitting 1s. During accesses to external

data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2

special function register. Some Port 2 pins receive the high order address bits during

EPROM programming and verification.

P3.0–P3.7

10–17

11,

13–19

7–13

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger

inputs. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and

can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source

current because of the pull-ups. (See DC Electrical Characteristics: I

). Port 3 also serves

the special features of the 80C51 family, as listed below:

RxD (P3.0): Serial input port

TxD (P3.1): Serial output port

INT0 (P3.2): External interrupt

INT1 (P3.3): External interrupt

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

RST

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the

device. An internal diffused resistor to V

permits a power-on reset using only an external

capacitor to V

ALE/PROG

Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the

address during an access to external memory. In normal operation, ALE is emitted at a

constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.

Note that one ALE pulse is skipped during each access to external data memory. This pin is

also the program pulse input (PROG) during EPROM programming. ALE can be disabled by

setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.

PSEN

Program Store Enable: The read strobe to external program memory. When the device is

executing code from the external program memory, PSEN is activated twice each machine

cycle, except that two PSEN activations are skipped during each access to external data

memory. PSEN is not activated during fetches from internal program memory.

EA/V

External Access Enable/Programming Supply Voltage: EA must be externally held low

to enable the device to fetch code from external program memory locations 0000H to

0FFFH. If EA is held high, the device executes from internal program memory unless the

program counter contains an address greater than the on-chip ROM/OTP. This pin also

receives the 12.75 V programming supply voltage (V

) during EPROM programming. If

security bit 1 is programmed, EA will be internally latched on Reset.

XTAL1

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator

circuits.

XTAL2

Crystal 2: Output from the inverting oscillator amplifier.

NOTE:

To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V

+ 0.5 V or V

– 0.5 V, respectively.