80C51 8-bit microcontroller family 2K/64 OTP/ROM, I<sup>2</sup> C, low pin count

Philips Semiconductors

Product specification

83C751/87C751

80C51 8-bit microcontroller family

2K/64 OTP/ROM, I

C, low pin count

1998 May 01

853-0599 19326

DESCRIPTION

The Philips 83C751/87C751 offers the advantages of the 80C51

architecture in a small package and at low cost.

The 8XC751 Microcontroller is fabricated with Philips high-density

CMOS technology. Philips epitaxial substrate minimizes CMOS

latch-up sensitivity.

The 8XC751 contains a 2k

8 ROM (83C751) EPROM (87C751), a

8 RAM, 19 I/O lines, a 16-bit auto-reload counter/timer, a

five-source, fixed-priority level interrupt structure, a bidirectional

inter-integrated circuit (I

C) serial bus interface, and an on-chip

oscillator.

The on-board inter-integrated circuit (I

C) bus interface allows the

8XC751 to operate as a master or slave device on the I

C small

area network. This capability facilitates I/O and RAM expansion,

access to EEPROM, processor-to-processor communication, and

efficient interface to a wide variety of dedicated I

C peripherals.

FEATURES

•

80C51 based architecture

•

Inter-Integrated Circuit (I

C) serial bus interface

•

Small package sizes

– 24-pin DIP (300 mil “skinny DIP”)

– 24-pin Shrink Small Outline Package

– 28-pin PLCC

•

87C751 available in one-time programmable plastic packages

•

Wide oscillator frequency range

•

Low power consumption:

– Normal operation: less than 11mA @ 5V, 12MHz

– Idle mode

– Power-down mode

•

8 ROM (83C751)

8 EPROM (87C751)

•

8 RAM

•

16-bit auto reloadable counter/timer

•

Fixed-rate timer

•

Boolean processor

•

CMOS and TTL compatible

•

Well suited for logic replacement, consumer and industrial

applications

•

LED drive outputs

PIN CONFIGURATIONS

P3.4/A4

P3.3/A3

P3.2/A2/A10

P3.1/A1/A9

P3.0/A0/A8

P0.2/V

P0.1/SDA/OE–PGM

RST

P0.0/SCL/ASEL

P1.0/D0

P1.1/D1

P1.2/D2

P1.3/D3

P1.4/D4

P1.5/INT0/D5

P1.6/INT1/D6

P1.7/T0/D7

P3.7/A7

P3.6/A6

P3.5/A5

PLASTIC

DUAL

IN-LINE

PACKAGE

AND

SHRINK

SMALL

OUTLINE

PACKAGE

PLASTIC

LEADED

CHIP

CARRIER

Pin

Function

P3.4/A4

P3.3/A3

P3.2/A2/A10

P3.1/A1/A9

NC*

P3.0/A0/A8

P0.2/V

P0.1/SDA/OE-PGM

P0.0//SCLASEL

SU00315

* DO NOT CONNECT

PinFunction

NC*

RST

P1.0/D0

P1.1/D1

P1.2/D2

P1.3/D3

Pin

Function

P1.4/D4

P1.5/INT0/D5

NC*

P1.6/INT1/D6

P1.7/T0/D7

P3.7/A7

P3.6/A6

P3.5/A5

Philips Semiconductors

Product specification

83C751/87C751

80C51 8-bit microcontroller family

2K/64 OTP/ROM, I

C, low pin count

1998 May 01

ORDERING INFORMATION

ROM

EPROM

TEMPERATURE RANGE

AND PACKAGE

FREQUENCY

DRAWING

NUMBER

S83C751–1N24

S87C751–1N24

OTP

0 to +70, Plastic Dual In-line Package

3.5 to 12MHz

SOT222-1

S83C751–2N24

S87C751–2N24

OTP

–40 to +85, Plastic Dual In-line Package

3.5 to 12MHz

SOT222-1

S83C751–4N24

S87C751–4N24

OTP

0 to +70, Plastic Dual In-line Package

3.5 to 16MHz

SOT222-1

S83C751–5N24

S87C751–5N24

OTP

–40 to +85, Plastic Dual In-line Package

3.5 to 16MHz

SOT222-1

S83C751–1A28

S87C751–1A28

OTP

0 to +70, Plastic Leaded Chip Carrier

3.5 to 12MHz

SOT261-3

S83C751–2A28

S87C751–2A28

OTP

–40 to +85, Plastic Leaded Chip Carrier

3.5 to 12MHz

SOT261-3

S83C751–4A28

S87C751–4A28

OTP

0 to +70, Plastic Leaded Chip Carrier

3.5 to 16MHz

SOT261-3

S83C751–5A28

S87C751–5A28

OTP

–40 to +85, Plastic Leaded Chip Carrier

3.5 to 16MHz

SOT261-3

S83C751–1DB

S87C751–1DB

OTP

0 to +70, Shrink Small Outline Package

3.5 to 12MHz

SOT340-1

S83C751–4DB

S87C751–4DB

OTP

0 to +70, Shrink Small Outline Package

3.5 to 16MHz

SOT340-1

NOTE:

1. OTP = One Time Programmable EPROM.

Philips Semiconductors

Product specification

83C751/87C751

80C51 8-bit microcontroller family

2K/64 OTP/ROM, I

C, low pin count

1998 May 01

PIN DESCRIPTIONS

PIN NO.

MNEMONIC

DIP/

SSOP

LCC

TYPE

NAME AND FUNCTION

Circuit Ground Potential

Supply voltage during normal, idle, and power-down operation.

P0.0–P0.2

8–6

9–7

I/O

Port 0: Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float,

and in that state can be used as high-impedance inputs. Port 0 also serves as the serial I

interface. When this feature is activated by software, SCL and SDA are driven low in accordance

with the I

C protocol. These pins are driven low if the port register bit is written with a 0 or if the I

subsystem presents a 0. The state of the pin can always be read from the port register by the

program.

To comply with the I

C specification, P0.0 and P0.1 are open drain bidirectional I/O pins with the

electrical characteristics listed in the tables that follow. While these differ from “standard TTL”

characteristics, they are close enough for the pins to still be used as general-purpose I/O in

non-I

C applications. Port 0 also provides alternate functions for programming the EPROM

memory as follows:

N/A

(P0.2) – Programming voltage input. (See Note 1.)

OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode.

OE/PGM = 1 output enabled (verify mode).

OE/PGM = 0 program mode.

ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.

ASEL = 0 low address byte available on port 3.

ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).

I/O

SDA (P0.1) – I

C data.

I/O

SCL (P0.0) – I

C clock.

P1.0–P1.7

13–20

15–20,

23, 24

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written

to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins

that are externally pulled low will source current because of the internal pull-ups. (See DC

Electrical Characteristics: I

). Port 1 serves to output the addressed EPROM contents in the verify

mode and accepts as inputs the value to program into the selected address during the program

mode. Port 1 also serves the special function features of the 80C51 family as listed below:

INT0 (P1.5): External interrupt.

INT1 (P1.6): External interrupt.

T0 (P1.7): Timer 0 external input.

P3.0–P3.7

5–1,

23–21

6, 4–1,

27–25

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written

to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins

that are externally being pulled low will source current because of the pull-ups. (See DC Electrical

Characteristics: I

). Port 3 also functions as the address input for the EPROM memory location to

be programmed (or verified). The 11-bit address is multiplexed into this port as specified by

P0.0/ASEL.

RST

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.

An internal diffused resistor to V

permits a power-on RESET using only an external capacitor to

. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places

the device in the programming state allowing programming address, data and V

to be applied for

programming or verification purposes. The RESET serial sequence must be synchronized with the

X1 input.

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.

X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the

programming state.

Crystal 2: Output from the inverting oscillator amplifier.

NOTE:

1. When P0.2 is at or close to 0V it may affect the internal ROM operation. We recommend that P0.2 be tied to V

via a small pullup

(e.g., 2k

Ω

Philips Semiconductors

Product specification

83C751/87C751

80C51 8-bit microcontroller family

2K/64 OTP/ROM, I

C, low pin count

1998 May 01

ABSOLUTE MAXIMUM RATINGS

1, 2

PARAMETER

RATING

UNIT

Storage temperature range

–65 to +150

Voltage from V

to V

–0.5 to +6.5

Voltage from any pin to V

(except V

)

–0.5 to V

+ 0.5

Power dissipation

1.0

Voltage on V

pin to V

0 to +13.0

Maximum I

per I/O pin

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section

of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

DC ELECTRICAL CHARACTERISTICS

amb

= 0

C to +70

C or –40

C to +85

C, V

= 5V

10% for 87C751, V

= 5V

10% for 83C751, V

= 0V

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Input low voltage, except SDA, SCL

–0.5

0.2V

–0.1

Input high voltage, except X1, RST

0.2V

+0.9

+0.5

IH1

Input high voltage, X1, RST

0.7V

+0.5

SDA, SCL, P0.2

IL1

Input low voltage

–0.5

0.3V

IH2

Input high voltage

0.7V

+0.5

Output low voltage, ports 1 and 3

= 1.6mA

0.45

OL1

Output low voltage, port 0.2

= 3.2mA

0.45

Output high voltage, ports 1 and 3

= –60

2.4

= –25

0.75V

= –10

0.9V

Port 0.0 and 0.1 (I

C) – Drivers

OL2

Output low voltage

= 3mA

0.4

Driver, receiver combined:

(over V

range)

Capacitance

Logical 0 input current, ports 1 and 3

= 0.45V

–50

Logical 1 to 0 transition current, ports 1 and 3

= 2V (0 to 70

= 2V (–40 to +85

–650

–750

Input leakage current, port 0

0.45 < V

< V

RST

Internal pull-down resistor

175

Ω

Pin capacitance

Test freq = 1MHz,

amb

= 25

Power-down current

= 2 to V

max

program voltage (for 87C751 only)

= 0V

= 5V

10%

amb

= 21

C to 27

12.5

13.0

Program current (for 87C751 only)

= 13.0V

Supply current (see Figure 2)

NOTES TO DC ELECTRICAL CHARACTERISTICS ON NEXT PAGE.

Philips Semiconductors

Product specification

83C751/87C751

80C51 8-bit microcontroller family

2K/64 OTP/ROM, I

C, low pin count

1998 May 01

NOTES TO DC ELECTRICAL CHARACTERISTICS:

1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

unless otherwise

noted.

2. Under steady state (non-transient) conditions, I

must be externally limited as follows:

Maximum I

per port pin:

10mA

(NOTE: This is 85

C spec.)

Maximum I

per 8-bit port:

26mA

Maximum total I

for all outputs:

67mA

If I

exceeds the test condition, V

may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

test conditions.

3. Pins of ports 1 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V

is approximately 2V.

4. Power-down I

is measured with all output pins disconnected; port 0 = V

; X2, X1 n.c.; RST = V

5. Active I

is measured with all output pins disconnected; X1 driven with t

CLCH

, t

CHCL

= 5ns, V

= V

+ 0.5V, V

= V

– 0.5V; X2 n.c.;

RST = port 0 = V

. I

will be slightly higher if a crystal oscillator is used.

6. Idle I

is measured with all output pins disconnected; X1 driven with t

CLCH

, t

CHCL

= 5ns, V

= V

+ 0.5V, V

= V

– 0.5V; X2 n.c.;

port 0 = V

; RST = V

AC ELECTRICAL CHARACTERISTICS

amb

= 0

C to +70

C or –40

C to +85

C, V

= 5V

10% for 87C751, V

= 5V

10% for 83C751, V

= 0V

1, 2

12MHz CLOCK

VARIABLE CLOCK

SYMBOL

PARAMETER

MIN

MAX

MIN

MAX

UNIT

1/t

CLCL

Oscillator frequency:

3.5

MHz

3.5

MHz

External Clock (Figure 1)

CHCX

High time

CLCX

Low time

CLCH

Rise time

CHCL

Fall time

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

unless otherwise

noted.

2. Load capacitance for ports = 80pF.

Philips Semiconductors

Product specification

83C751/87C751

80C51 8-bit microcontroller family

2K/64 OTP/ROM, I

C, low pin count

1998 May 01

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always

‘t’ (= time). The other characters, depending on their positions,

indicate the name of a signal or the logical status of that signal. The

designations are:

C –

Clock

D –

Input data

H –

Logic level high

–

Logic level low

Q –

Output data

T –

Time

V –

Valid

X –

No longer a valid logic level

Z –

Float

CHCL

CLCL

CLCH

CHCX

–0.5

0.45V

0.2 V

+ 0.9

0.2 V

– 0.1

CLCX

SU00297

Figure 1. External Clock Drive

4MHz

8MHz

12MHz

16MHz

FREQ

MAX ACTIVE ICC

TYP ACTIVE ICC

MAX IDLE ICC

TYP IDLE ICC

ICC (mA)

SU00298

Figure 2. I

vs. FREQ

Maximum I

values taken at V

max and worst case temperature.

Typical I

values taken at V

= 5.0V and 25

Notes 5 and 6 refer to DC Electrical Characteristics.

Philips Semiconductors

Product specification

83C751/87C751

80C51 8-bit microcontroller family

2K/64 OTP/ROM, I

C, low pin count

1998 May 01

OSCILLATOR CHARACTERISTICS

X1 and X2 are the input and output, respectively, of an inverting

amplifier which can be configured for use as an on-chip oscillator.

To drive the device from an external clock source, X1 should be

driven while X2 is left unconnected. There are no requirements on

the duty cycle of the external clock signal, because the input to the

internal clock circuitry is through a divide-by-two flip-flop. However,

minimum and maximum high and low times specified in the data

sheet must be observed.

RESET

A reset is accomplished by holding the RST pin high for at least two

machine cycles (24 oscillator periods), while the oscillator is running.

To insure a good power-up reset, the RST pin must be high long

enough to allow the oscillator time to start up (normally a few

milliseconds) plus two machine cycles. At power-up, the voltage on

and RST must come up at the same time for a proper start-up.

IDLE MODE

In idle mode, the CPU puts itself to sleep while all of the on-chip

peripherals stay active. The instruction to invoke the idle mode is the

last instruction executed in the normal operating mode before the

idle mode is activated. The CPU contents, the on-chip RAM, and all

of the special function registers remain intact during this mode. The

idle mode can be terminated either by any enabled interrupt (at

which time the process is picked up at the interrupt service routine

and continued), or by a hardware reset which starts the processor in

the same manner as a power-on reset.

POWER-DOWN MODE

In the power-down mode, the oscillator is stopped and the

instruction to invoke power-down is the last instruction executed.

Only the contents of the on-chip RAM are preserved. A hardware

reset is the only way to terminate the power-down mode. the control

bits for the reduced power modes are in the special function register

PCON.

Table 1.

External Pin Status During Idle and

Power-Down Modes

MODE

Port 0

Port 1

Port 2

Idle

Data

Power-down

Data

DIFFERENCES BETWEEN THE 8XC751 AND THE

80C51

Memory Organization

The central processing unit (CPU) manipulates operands in two

address spaces as shown in Figure 3. The part’s internal memory

space consists of 2k bytes of program memory, and 64 bytes of data

RAM overlapped with the 128-byte special function register area.

The differences from the 80C51 are in RAM size (64 bytes vs. 128

bytes), in external RAM access (not available on the 83C751), in

internal ROM size (2k bytes vs. 4k bytes), and in external program