PORT 0
PORT 1
PORT 2
PORT 3
ADDRESS AND
DA
T
A
BUS
ADDRESS BUS
VSS
VDD
AL
TERNA
TE
FUNCTIONS
RST
XTAL1
XTAL2
ALE
PSEN
RxD
TxD
INT0
INT1
T0
T1
WR
RD
SCL
SDA
EA
Phlips Semiconductors
Product specification
80C652/83C652
CMOS single-chip 8-bit microcontrollers
2
1997 Dec 05
DESCRIPTION
The P80C652/83C652 Single-Chip 8-Bit
Microcontroller is manufactured in an
advanced CMOS process and is a derivative
of the 80C51 microcontroller family. The
80C652/83C652 has the same instruction set
as the 80C51. Three versions of the
derivative exist:
83C652 — 8k bytes mask programmable
ROM
80C652 — ROMless version
87C652 — EPROM version (described in a
separate chapter)
This device provides architectural
enhancements that make it applicable in a
variety of applications for general control
systems. The 8XC652 contains a non-volatile
8k
×
8 read-only program memory, a volatile
256
×
8 read/write data memory, four 8-bit I/O
ports, two 16-bit timer/event counters
(identical to the timers of the 80C51), a
multi-source, two-priority-level, nested
interrupt structure, an I
2
C interface, UART
and on-chip oscillator and timing circuits. For
systems that require extra capability, the
8XC652 can be expanded using standard
TTL compatible memories and logic.
The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte and 17
three-byte. With a 16(24)MHz crystal, 58% of
the instructions are executed in 0.75(0.5)
µ
s
and 40% in 1.5(1)
µ
s. Multiply and divide
instructions require 3(2)
µ
s.
LOGIC SYMBOL
FEATURES
•
80C51 central processing unit
•
8k
×
8 ROM expandable externally to
64k bytes
•
256
×
8 RAM, expandable externally to
64k bytes
•
Two standard 16-bit timer/counters
•
Four 8-bit I/O ports
•
I
2
C-bus serial I/O port with byte oriented
master and slave functions
•
Full-duplex UART facilities
•
Power control modes
– Idle mode
– Power-down mode
•
ROM code protection
•
Extended frequency range: 3.5 to 24 MHz
•
Three operating ambient temperature
ranges:
0 to +70
°
C
–40 to +85
°
C
–40 to +125
°
C
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
SCL/P1.6
RST
RxD/P3.0
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
SDA/P1.7
RD/P3.7
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
6
1
40
7
17
39
29
18
28
44
34
1
11
33
23
12
22
WR/P3.6
PLASTIC
DUAL
IN-LINE
PACKAGE
PLASTIC
LEADED
CHIP
CARRIER
PLASTIC
QUAD
FLAT
PACK
Phlips Semiconductors
Product specification
80C652/83C652
CMOS single-chip 8-bit microcontrollers
1997 Dec 05
4
ORDER INFORMATION
PHILIPS
PART ORDER NUMBER
PART MARKING
PHILIPS NORTH AMERICA
PART ORDER NUMBER
TEMPERATURE RANGE
(
°
C)
FREQ
MH
1 2
ROMless
ROM
3
Drawing
Number
ROMless
ROM
EPROM
2
(
)
AND PACKAGE
MHz
1,2
P80C652EBP
P83C652EBP/xxx
SOT129-1
P80C652EBPN
P83C652EBPN
S87C652-4N40
0 to +70,
Plastic Dual In-line Package
16
P80C652EBA
P83C652EBA/xxx
SOT187-2
P80C652EBAA
P83C652EBAA
S87C652-4A44
0 to +70,
Plastic Leaded Chip Carrier
16
P80C652EBB
P83C652EBB/xxx
SOT307-2
P80C652EBBB
P83C652EBBB
S87C652-4B44
0 to +70,
Plastic Quad Flat Pack
16
P80C652EFP
P83C652EFP/xxx
SOT129-1
P80C652EFPN
P83C652EFPN
S87C652-5N40
–40 to +85,
Plastic Dual In-line Package
16
P80C652EFA
P83C652EFA/xxx
SOT187-2
P80C652EFAA
P83C652EFAA
S87C652-5A44
–40 to +85,
Plastic Leaded Chip Carrier
16
P80C652EFB
P83C652EFB/xxx
SOT307-2
P80C652EFBB
P83C652EFBB
S87C652-5B44
–40 to +85,
Plastic Quad Flat Pack
16
P80C652EHP
P83C652EHP/xxx
SOT129-1
P80C652EHPN
P83C652EHPN
–40 to +125,
Plastic Dual In-line Package
16
P80C652EHA
P83C652EHA/xxx
SOT187-2
P80C652EHAA
P83C652EHAA
–40 to +125,
Plastic Leaded Chip Carrier
16
P80C652EHB
P83C652EHB/xxx
SOT307-2
P80C652EHBB
P83C652EHBB
–40 to +125,
Plastic Quad Flat Pack
16
P80C652IBP
P83C652IBP/xxx
SOT129-1
P80C652IBPN
P83C652IBPN
0 to +70,
Plastic Dual In-line Package
24
P80C652IBA
P83C652IBA/xxx
SOT187-2
P80C652IBAA
P83C652IBAA
0 to +70,
Plastic Leaded Chip Carrier
24
P80C652IBB
P83C652IBB/xxx
SOT307-2
P80C652IBBB
P83C652IBBB
0 to +70,
Plastic Quad Flat Pack
24
P80C652IFP
P83C652IFP/xxx
SOT129-1
P80C652IFPN
P83C652IFPN
–40 to +85,
Plastic Dual In-line Package
24
P80C652IFA
P83C652IFA/xxx
SOT187-2
P80C652IFAA
P83C652IFAA
–40 to +85,
Plastic Leaded Chip Carrier
24
P80C652IFB
P83C652IFB/xxx
SOT307-2
P80C652IFBB
P83C652IFBB
–40 to +85,
Plastic Quad Flat Pack
24
NOTES:
1. 80C652 and 83C652 frequency range is 3.5MHz–16MHz or 3.5MHz–24MHz.
2. For specification of the EPROM version, see the 87C652 data sheet.
3. xxx denotes the ROM code number.
Phlips Semiconductors
Product specification
80C652/83C652
CMOS single-chip 8-bit microcontrollers
1997 Dec 05
6
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC
DIP
PLCC
QFP
TYPE
NAME AND FUNCTION
V
SS
20
22
6, 16,
28, 39
I
Ground: 0V reference. With the QFP package all V
SS
pins (V
SS1
to V
SS4
) must be
connected.
V
DD
40
44
38
I
Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
P0.0–0.7
39–32
43–36
37–30
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s.
P1.0–P1.7
1–8
2–9
40–44,
1–3
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7
which are open drain. Port 1 pins that have 1s written to them are pulled high by the
internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled
low will source current because of the internal pull-ups. (See DC Electrical Characteristics:
I
IL
). Alternate functions include:
P1.6
7
8
2
I/O
SCL: I
2
C-bus serial port clock line.
P1.7
8
9
3
I/O
SDA: I
2
C-bus serial port data line.
P2.0–P2.7
21–28
24–31
18–25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: I
IL
). Port 2 emits the high-order
address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.
P3.0–P3.7
10–17
11,
13–19
5,
7–13
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: I
IL
). Port 3 also serves the special features of
the 80C51 family, as listed below:
10
11
5
I
RxD (P3.0): Serial input port
11
13
7
O
TxD (P3.1): Serial output port
12
14
8
I
INT0 (P3.2): External interrupt
13
15
9
I
INT1 (P3.3): External interrupt
14
16
10
I
T0 (P3.4): Timer 0 external input
15
17
11
I
T1 (P3.5): Timer 1 external input
16
18
12
O
WR (P3.6): External data memory write strobe
17
19
13
O
RD (P3.7): External data memory read strobe
RST
9
10
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V
SS
permits a power-on reset using only an external
capacitor to V
DD
.
ALE
30
33
27
I/O
Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency. Note that one ALE pulse is skipped during each access to external
data memory.
PSEN
29
32
26
O
Program Store Enable: Read strobe to external program memory via Port 0 and Port 2. It
is activated twice each machine cycle during fetches from the external program memory.
When executing out of external program memory two activations of PSEN are skipped
during each access to external data memory. PSEN is not activated (remains HIGH) during
no fetches from external program memory. PSEN can sink/source 8 LSTTL inputs and can
drive CMOS inputs without external pull–ups.
EA
31
35
29
I
External Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out
of the internal program memory ROM provided the Program Counter is less than 8192. If
during a RESET, EA is held a TTL LOW level, the CPU executes out of external program
memory. EA is not allowed to float.
XTAL1
19
21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2
18
20
14
O
Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V
DD
+ 0.5V or V
SS
– 0.5V, respectively.
