atmel+�c_black

Rev. F - 15 February, 2001

T89C51RD2

0 to 40MHz Flash Programmable 8-bit Microcontroller

1. Description

ATMEL Wireless and Microcontrollers T89C51RD2 is

high performance CMOS Flash version of the 80C51

CMOS single chip 8-bit microcontroller. It contains a

64 Kbytes Flash memory block for program and for data.

The 64 Kbytes Flash memory can be programmed either

in parallel mode or in serial mode with the ISP capability

or with software. The programming voltage is internally

generated from the standard V

pin.

The T89C51RD2 retains all features of the ATMEL

Wireless and Microcontrollers 80C52 with 256 bytes of

internal RAM, a 7-source 4-level interrupt controller and

three timer/counters.

In addition, the T89C51RD2 has a Programmable

Counter Array, an XRAM of 1024 bytes, an EEPROM

of 2048 bytes, a Hardware Watchdog Timer, a more

versatile serial channel that facilitates multiprocessor

communication (EUART) and a speed improvement

mechanism (X2 mode). Pinout is either the standard 40/

44 pins of the C52 or an extended version with 6 ports

in a 64/68 pins package.

The fully static design of the T89C51RD2 allows to

reduce system power consumption by bringing the clock

frequency down to any value, even DC, without loss of

data.

The T89C51RD2 has 2 software-selectable modes of

reduced

activity

for

further

reduction

power

consumption. In the idle mode the CPU is frozen while

the peripherals and the interrupt system are still

operating. In the power-down mode the RAM is saved

and all other functions are inoperative.

The added features of the T89C51RD2 makes it more

powerful for applications that need

pulse width

modulation, high speed I/O and counting capabilities

such as alarms, motor control, corded phones, smart card

readers.

2. Features

•

80C52 Compatible

•

8051 pin and instruction compatible

•

Four 8-bit I/O ports (or 6 in 64/68 pins packages)

•

Three 16-bit timer/counters

•

256 bytes scratch pad RAM

•

7 Interrupt sources with 4 priority levels

•

ISP (In System Programming) using standard V

power supply.

•

Boot

FLASH

contains

low

level

FLASH

programming routines and a default serial loader

•

High-Speed Architecture

•

40 MHz in standard mode

•

20 MHz in X2 mode (6 clocks/machine cycle)

•

64K bytes on-chip Flash program / data Memory

•

Byte and page (128 bytes) erase and write

•

10k write cycles

•

On-chip 1024 bytes expanded RAM (XRAM)

•

Software selectable size (0, 256, 512, 768, 1024

bytes)

•

768 bytes selected at reset for T87C51RD2

compatibility

•

Dual Data Pointer

•

Variable length MOVX for slow RAM/peripherals

•

Improved X2 mode with independant selection for

CPU and each peripheral

•

2 k bytes EEPROM block for data storage

•

100K Write cycle

•

Programmable Counter Array with:

•

High Speed Output,

•

Compare / Capture,

•

Pulse Width Modulator,

•

Watchdog Timer Capabilities

•

Asynchronous port reset

•

Full duplex Enhanced UART

•

Low EMI (inhibit ALE)

•

Hardware Watchdog Timer (One-time enabled with

Reset-Out)

•

Power control modes:

•

Idle Mode.

•

Power-down mode.

Rev. F - 15 February, 2001

T89C51RD2

•

Power supply:

- M version: Commercial and industrial

4.5V to 5.5V : 40MHz X1 Mode, 20MHz X2 Mode

3V to 5.5V : 33MHz X1 Mode, 16 MHz X2 Mode

- L version: Commercial and industrial

2.7V to 3.6V : 25MHz X1 Mode, 12MHz X2 Mode

•

Temperature ranges: Commercial (0 to +70

C) and industrial (-40 to +85

C).

•

Packages: PDIL40, PLCC44, VQFP44, PLCC68, VQFP64

Table 1. Memory Size

3. Block Diagram

PDIL40

PLCC44

VQFP44 1.4

Flash (bytes)

EEPROM (bytes)

XRAM (bytes)

TOTAL RAM

(bytes)

I/O

T89C51RD2

64k

1024

1280

PLCC68

VQFP64 1.4

Flash (bytes)

EEPROM

(bytes)

XRAM (bytes)

TOTAL RAM

(bytes)

I/O

T89C51RD2

64k

1024

1280

Timer 0

INT

RAM

256x8

RxD

TxD

PSEN

ALE/

XTAL2

XTAL1

EUART

CPU

Timer 1

INT1

Ctrl

INT0

(3)

C51

CORE

(3) (3)

Port 0

Port 1 Port 2 Port 3

Parallel I/O Ports & Ext. Bus

XRAM

1Kx8

IB-bus

PCA

RESET

PROG

Watch

Dog

PCA

ECI

Vss

(3)

(1)

(1): Alternate function of Port 1

(3): Alternate function of Port 3

(1)

Timer2

T2EX

(1)

Port 5

Port 4

(2): Only available on high pin count packages

(2)

Flash

64Kx8

EEPROM

2Kx8

Rev. F - 15 February, 2001

T89C51RD2

4. SFR Mapping

The Special Function Registers (SFRs) of the T89C51RD2 fall into the following categories:

•

C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1

•

I/O port registers: P0, P1, P2, P3, P4, P5

•

Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H

•

Serial I/O port registers: SADDR, SADEN, SBUF, SCON

•

Power and clock control registers: PCON

•

Hardware Watchdog Timer register: WDTRST, WDTPRG

•

Interrupt system registers: IE, IP, IPH

•

Flash and EEPROM registers: FCON, EECON, EETIM

•

Others: AUXR, AUXR1, CKCON

Table below shows all SFRs with their address and their reset value.

Bit

address-

able

Non Bit addressable

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

F8h

0000 0000

CCAP0H

XXXX XXXX

CCAP1H

XXXX XXXX

CCAPL2H

XXXX XXXX

CCAPL3H

XXXX XXXX

CCAPL4H

XXXX XXXX

FFh

F0h

0000 0000

F7h

E8h

1111 1111

0000 0000

CCAP0L

XXXX XXXX

CCAP1L

XXXX XXXX

CCAPL2L

XXXX XXXX

CCAPL3L

XXXX XXXX

CCAPL4L

XXXX XXXX

EFh

E0h

ACC

0000 0000

E7h

D8h

CCON

00X0 0000

CMOD

00XX X000

CCAPM0

X000 0000

CCAPM1

X000 0000

CCAPM2

X000 0000

CCAPM3

X000 0000

CCAPM4

X000 0000

DFh

D0h

PSW

0000 0000

FCON

XXXX 0000

EECON

XXXX XX00

EETIM

0000 0000

D7h

C8h

T2CON

0000 0000

T2MOD

XXXX XX00

RCAP2L

0000 0000

RCAP2H

0000 0000

TL2

0000 0000

TH2

0000 0000

CFh

C0h

1111 1111

C7h

B8h

X000 000

SADEN

0000 0000

BFh

B0h

1111 1111

IPH

X000 0000

B7h

A8h

0000 0000

SADDR

0000 0000

AFh

A0h

1111 1111

AUXR1

XXXX 00X0

WDTRST

XXXX XXXX

WDTPRG

XXXX X000

A7h

98h

SCON

0000 0000

SBUF

XXXX XXXX

9Fh

90h

1111 1111

97h

88h

TCON

0000 0000

TMOD

0000 0000

TL0

0000 0000

TL1

0000 0000

TH0

0000 0000

TH1

0000 0000

AUXR

XX0X 1000

CKCON

X000 0000

8Fh

80h

1111 1111

0000 0111

DPL

0000 0000

DPH

0000 0000

PCON

00X1 0000

87h

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

Rev. F - 15 February, 2001

T89C51RD2

5. Pin Configuration

P1.7CEX4

P1.4/CEX1

RST

P3.0/RxD

P3.1/TxD

P1.3CEX0

P1.5/CEX2

P1.6/CEX3

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

VSS

P2.0/AD8

P2.1/AD9

P2.2/AD10

P2.3/AD11

P2.4/AD12

P0.4/AD4

P0.6/AD6

P0.5/AD5

P0.7/AD7

ALE/PROG

PSEN

P2.7/AD15

P2.5/AD13

P2.6/AD14

P1.0/T2

P1.2/ECI

P1.1/T2EX

VCC

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3

PDIL

18 19

27 28

5 4 3 2 1

44 43 42 41 40

P1.4/CEX1

P1.0/T2

P1.1/T2EX

P1.3/CEX0

P1.2/ECI

VSS1/NIC*

VCC

P0.0/AD0

P0.2/AD2

P0.1/AD1

P0.4/AD4

P0.6/AD6

P0.5/AD5

P0.7/AD7

ALE/PROG

PSEN

NIC*

P2.7/A15

P2.5/A13

P2.6/A14

P3.6/WR

P3.7/RD

AL2

AL1

VSS

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

43 42 41 40 39

38 37 36 35 34

P1.4/CEX1

P1.0/T2

P1.1/T2EX

P1.3/CEX0

P1.2/ECI

VSS1/NIC*

VCC

P0.0/AD0

P0.2/AD2

P0.3/AD3

P0.1/AD1

P0.4/AD4

P0.6/AD6

P0.5/AD5

P0.7/AD7

ALE/PROG

PSEN

NIC*

P2.7/A15

P2.5/A13

P2.6/A14

P1.5/CEX2

P1.6/CEX3

P1.7/CEX4

RST

P3.0/RxD

NIC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

AL2

AL1

VSS

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P1.5/CEX2

P1.6/CEX3

P1.7/CEx4

RST

P3.0/RxD

NIC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P0.3/AD3

NIC*

*NIC: No Internal Connection

PLCC

12 13

21 22

VQFP44 1.4

Rev. F - 15 February, 2001

T89C51RD2

P5.5

P0.3/AD3

P0.2/AD2

P5.6

P0.1/AD1

P0.0/AD0

P5.7

VCC

VSS1

P1.0/T2

P4.0

P1.1/T2EX

P1.2/ECI

P1.3/CEX0

P4.1

P1.4/CEX1

P4.2

1 68 67 66 65 64 63

36 37 38 39 40 41

29 30 31 32 33 34 35

27 28

42 43

PSEN

P5.3

P0.5/AD5

P0.6/AD6

NIC

P0.7/AD7

NIC

ALE/PRO

NIC

P2.7/A15

P2.6/A14

P5.2

P0.4/AD4

P5.4

P5.1

P2.5/A13

NIC

P1.7/CEX4

RST

NIC

P3.0/RxD

NIC

P3.1/TxD

P3.3/INT1

P5.0

P2.4/A12

P2.3/A11

P4.7

P2.2/A10

P2.1/A9

P2.0/A8

VSS

P4.6

P4.5

XTAL1

XTAL2

NIC

PLCC 68

62 61

P1.5/CEX2

P1.6/CEX3

P3.4/T0

P3.5/T1

P4.4

P3.6/WR

P4.3

P3.7/RD

P3.2/INT0

PSEN

P5.4

P5.3

P0.5/AD5

P0.6/AD6

P0.7/AD7

NIC

ALE/PROG

P2.7/A15

P2.6/A14

P5.2

P5.1

P2.5/A13

P5.0

P0.4/AD4

VSS

P2.3/A11

P4.7

P2.2/A10

P2.1/A9

P2.0/A8

P4.6

P4.5

NIC

XTAL1

XTAL2

P3.7/RD

P4.4

P4.3

P2.4/A12

P3.6/WR

P1.0/T2

P0.3/AD3

P0.2/AD2

P5.6

P0.1/AD1

P0.0/AD0

P5.7

VCC

VSS1

P4.0

P1.1/T2EX

P1.2/EC1

P1.3/CEX0

P4.1

P1.4/CEX1

P5.5

NIC

P3.4/T0

P3.2/INT0

P3.1/TxD

NIC

P3.0/RxD

NIC

RST

P1.7/CEX4

P1.6/CEX3

P1.5/CEX2

P4.2

P3.5/T1

18 19 20 21 22 23 24 25

27 28 29 30 31 32

VQFP64 1.4

P3.3/INT1

NIC: No InternalConnection

Rev. F - 15 February, 2001

T89C51RD2

Mnemonic

Pin Number

Type

Name and Function

DIL

LCC

VQFP 1.4

Ground: 0V reference

Vss1

Optional Ground: Contact the Sales Office for ground connection.

Power Supply: This is the power supply voltage for normal, idle and power-

down operation

P0.0-P0.7

39-32

43-36

37-30

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s

written to them float and can be used as high impedance inputs. Port 0 must be

polarized to V

or V

in order to prevent any parasitic current consumption.

Port 0 is also the multiplexed low-order address and data bus during access to

external program and data memory. In this application, it uses strong internal

pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM

programming. External pull-ups are required during program verification during

which P0 outputs the code bytes.

P1.0-P1.7

1-8

2-9

40-44

1-3

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins

that have 1s written to them are pulled high by the internal pull-ups and can be

used as inputs. As inputs, Port 1 pins that are externally pulled low will source

current because of the internal pull-ups. Port 1 also receives the low-order address

byte during memory programming and verification.

Alternate functions for TSC8x54/58 Port 1 include:

I/O

T2 (P1.0): Timer/Counter 2 external count input/Clockout

T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control

ECI (P1.2): External Clock for the PCA

I/O

CEX0 (P1.3): Capture/Compare External I/O for PCA module 0

I/O

CEX1 (P1.4): Capture/Compare External I/O for PCA module 1

I/O

CEX2 (P1.5): Capture/Compare External I/O for PCA module 2

I/O

CEX3 (P1.6): Capture/Compare External I/O for PCA module 3

I/O

CEX4 (P1.7): Capture/Compare External I/O for PCA module 4

P2.0-P2.7

21-28

24-31

18-25

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2

pins that have 1s written to them are pulled high by the internal pull-ups and

can be used as inputs. As inputs, Port 2 pins that are externally pulled low will

source current because of the internal pull-ups. Port 2 emits the high-order address

byte during fetches from external program memory and during accesses to external

data memory that use 16-bit addresses (MOVX @DPTR).In this application, it

uses strong internal pull-ups emitting 1s. During accesses to external data memory

that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.

Some Port 2 pins receive the high order address bits during EPROM programming

and verification:

P2.0 to P2.5 for RB devices

P2.0 to P2.6 for RC devices

P2.0 to P2.7 for RD devices.

P3.0-P3.7

10-17

11,

13-19

7-13

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins

that have 1s written to them are pulled high by the internal pull-ups and can be

used as inputs. As inputs, Port 3 pins that are externally pulled low will source

current because of the internal pull-ups. Port 3 also serves the special features

of the 80C51 family, as listed below.

RXD (P3.0): Serial input port

TXD (P3.1): Serial output port

INT0 (P3.2): External interrupt 0

INT1 (P3.3): External interrupt 1

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

WR (P3.6): External data memory write strobe

Rev. F - 15 February, 2001

T89C51RD2

Mnemonic

Pin Number

Type

Name and Function

DIL

LCC

VQFP 1.4

RD (P3.7): External data memory read strobe

Reset

I/O

Reset: A high on this pin for two machine cycles while the oscillator is running,

resets the device. An internal diffused resistor to V

permits a power-on reset

using only an external capacitor to V

. This pin is an output when the hardware

watchdog forces a system reset.

ALE/PROG

O (I)

Address Latch Enable/Program Pulse: Output pulse for latching the low byte

of the address during an access to external memory. In normal operation, ALE

is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,

and can be used for external timing or clocking. Note that one ALE pulse is

skipped during each access to external data memory. This pin is also the program

pulse input (PROG) during Flash programming. ALE can be disabled by setting

SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches.

PSEN

Program Store ENable: The read strobe to external program memory. When

executing code from the external program memory, PSEN is activated twice each

machine cycle, except that two PSEN activations are skipped during each access

to external data memory. PSEN is not activated during fetches from internal

program memory.

External Access Enable: EA must be externally held low to enable the device

to fetch code from external program memory locations 0000H to FFFFH (RD).

If security level 1 is programmed, EA will be internally latched on Reset.

XTAL1

Crystal 1: Input to the inverting oscillator amplifier and input to the internal

clock generator circuits.

XTAL2

Crystal 2: Output from the inverting oscillator amplifier