TPS3836E18 / J25 / H30 / L30 / K33
TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33
NANOPOWER SUPERVISORY CIRCUITS
SLVS292A – JUNE 2000 – REVISED JANUARY 2002
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D
Supply Current of 220 nA (Typ)
D
Precision Supply Voltage Supervision
Range: 1.8 V, 2.5 V, 3.0 V, 3.3 V
D
Power-On Reset Generator With Selectable
Delay Time of 10 ms or 200 ms
D
Push/Pull RESET Output (TPS3836),
RESET Output (TPS3837), or
Open-Drain RESET Output (TPS3838)
D
Manual Reset
D
5-Pin SOT-23 Package
D
Temperature Range –40
°
C to 85
°
C
D
Applications Include
– Applications Using Low-Power DSPs,
Microcontrollers, or Microprocessors
– Portable/Battery-Powered Equipment
– Intelligent Instruments
– Wireless Communication Systems
– Notebook Computers
– Automotive Systems
description
The TPS3836, TPS3837, TPS3838 families of
supervisory circuits provide circuit initialization
and timing supervision, primarily for DSP and
processor-based systems.
During power on, RESET is asserted when the
supply voltage V
DD
becomes higher than 1.1 V.
Thereafter, the supervisory circuit monitors V
DD
and keeps RESET output active as long as V
DD
remains below the threshold voltage V
IT
. An
internal timer delays the return of the output to the
inactive state (high) to ensure proper system
reset. The delay time starts after V
DD
has risen
above the threshold voltage V
IT
.
When CT is connected to GND a fixed delay time of typical 10 ms is asserted. When connected to V
DD
the delay
time is typically 200 ms.
When the supply voltage drops below the threshold voltage V
IT
, the output becomes active (low) again.
All the devices of this family have a fixed-sense threshold voltage V
IT
set by an internal voltage divider.
The TPS3836 has an active-low push-pull RESET output. The TPS3837 has active-high push-pull RESET, and
TPS3838 integrates an active-low open-drain RESET output.
VDD
GND
CT
MR
RESET
TPS3836K33
VCC
VSS
RST
Xin
MSP430
Xout
T
Quartz
32 kHz
Lithium
Battery
3.6 V
TYPICAL OPERATING CIRCUIT
Copyright
2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3
2
4
5
(TOP VIEW)
1
CT
GND
MR
VDD
RESET
TPS3836, TPS3838
DBV PACKAGE
3
2
4
5
(TOP VIEW)
1
CT
GND
MR
VDD
RESET
TPS3837
DBV PACKAGE
TPS3836E18 / J25 / H30 / L30 / K33
TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33
NANOPOWER SUPERVISORY CIRCUITS
SLVS292A – JUNE 2000 – REVISED JANUARY 2002
2
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description (continued)
The product spectrum is designed for supply voltages of 1.8 V, 2.5 V, 3 V, and 3.3 V. The circuits are available
in a 5-pin SOT-23 package. The TPS3836, TPS3837, TPS3838 families are characterized for operation over
a temperature range of –40
°
C to 85
°
C.
PACKAGE INFORMATION
TA
DEVICE NAME
THRESHOLD VOLTAGE
SYMBOL
TPS3836E18DBVR†
TPS3836E18DBVT‡
1.71 V
PDNI
TPS3836J25DBVR†
TPS3836J25DBVT‡
2.25 V
PDSI
TPS3836H30DBVR†
TPS3836H30DBVT‡
2.79 V
PHRI
TPS3836L30DBVR†
TPS3836L30DBVT‡
2.64 V
PCAI
TPS3836K33DBVR†
TPS3836K33DBVT‡
2.93 V
PDTI
TPS3837E18DBVR†
TPS3837E18DBVT‡
1.71 V
PDOI
–40
°
C to 85
°
C
TPS3837J25DBVR†
TPS3837J25DBVT‡
2.25 V
PDRI
40 C to 85 C
TPS3837L30DBVR†
TPS3837L30DBVT‡
2.64 V
PCBI
TPS3837K33DBVR†
TPS3837K33DBVT‡
2.93 V
PDUI
TPS3838E18DBVR†
TPS3838E18DBVT‡
1.71 V
PDQI
TPS3838J25DBVR†
TPS3838J25DBVT‡
2.25 V
PDPI
TPS3838L30DBVR†
TPS3838L30DBVT‡
2.64 V
PCCI
TPS3838K33DBVR†
TPS3838K33DBVT‡
2.93 V
PDVI
† The DBVR passive indicates tape and reel of 3000 parts.
‡ The DBVT passive indicates tape and reel of 250 parts.
ORDERING INFORMATION
TPS383 6 E 18 DBV R
Reel
Package
Nominal Supply Voltage
Typical Reset Threshold Voltage
Functionality
Family
FUNCTION TABLE TPS3836, TPS3837, TPS3838
MR
VDD > VIT
RESET§
RESET¶
L
0
L
H
L
1
L
H
H
0
L
H
H
1
H
L
§ TPS3836 and TPS3838
¶ TPS3837
TPS3836E18 / J25 / H30 / L30 / K33
TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33
NANOPOWER SUPERVISORY CIRCUITS
SLVS292A – JUNE 2000 – REVISED JANUARY 2002
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functional block diagram
Reset (TPS3837-Push-Pull)
Band-Gap
Reference
S3
S2
R2
R1
S1
C2
C1
C3
R3
–
+
Refresh
Timer
Reset Logic
and Timer
VDD
MR
GND
Reset (TPS3836-Push-Pull
TPS3838-Open-Drain)
CT
TPS3836E18 / J25 / H30 / L30 / K33
TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33
NANOPOWER SUPERVISORY CIRCUITS
SLVS292A – JUNE 2000 – REVISED JANUARY 2002
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timing diagram
td
t
RESET
t
t
td
td
MR
VDD
VIT
< 1.1 V
A
B
C
D
E
F
G
Undefined
Output
Undefined
Output
TPS3836E18 / J25 / H30 / L30 / K33
TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33
NANOPOWER SUPERVISORY CIRCUITS
SLVS292A – JUNE 2000 – REVISED JANUARY 2002
5
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
DD
(see Note 1)
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All other pins (see Note 1)
–0.3 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum low output current, I
OL
5 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum high output current, I
OH
–5 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
DD
)
±
10 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
DD
)
±
10 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation
See Dissipation Rating Table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
–40
°
C to 85
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soldering temperature
260
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND. For reliable operation, the device must not be operated at 7 V for more than t=1000 h
continuously
DISSIPATION RATING TABLE
PACKAGE
TA <25
°
C
POWER RATING
DERATING FACTOR
ABOVE TA = 25
°
C
TA = 70
°
C
POWER RATING
TA = 85
°
C
POWER RATING
DBV
437 mW
3.5 mW/ºC
280 mW
227 mW
recommended operating conditions at specified temperature range
MIN
MAX
UNIT
Supply voltage, VDD
1.6
6
V
Input voltage, VI
0
VDD + 0.3
V
High-level input voltage, VIH
0.7
×
VDD
V
Low-level input voltage, VIL
0.3
×
VDD
V
Input transition rise and fall rate at MR,
∆
t/
∆
V
100
ns/V
Operating free-air temperature range, TA
–40
85
°
C
TPS3836E18 / J25 / H30 / L30 / K33
TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33
NANOPOWER SUPERVISORY CIRCUITS
SLVS292A – JUNE 2000 – REVISED JANUARY 2002
6
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electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
RESET
VDD = 3.3 V,
IOH = –2 mA
V
High level output voltage
RESET
(TPS3836)
VDD = 6 V,
IOH = –3 mA
0.8
×
V
VOH
High-level output voltage
RESET
VDD = 1.8 V,
IOH = –1 mA
0.8
×
VDD
V
RESET
(TPS3837)
VDD = 3.3 V,
IOL = –2 mA
DD
RESET
VDD = 1.8 V,
IOL = 1 mA
V
Low level output voltage
RESET
(TPS3836/8)
VDD = 3.3 V,
IOL = 2 mA
0 4
V
VOL
Low-level output voltage
RESET
VDD = 3.3 V,
IOL = 2 mA
0.4
V
RESET
(TPS3837)
VDD = 6 V,
IOL = 3 mA
Power up reset voltage
TPS3836/8
VDD
≥
1.1 V,
IOL = 50
µ
A
0.2
Power-up reset voltage
(see Note 2)
TPS3837
VDD
≥
1.1 V,
IOH = –50
µ
A
0.8
×
VDD
V
TPS383xE18
1.66
1.71
1.74
N
ti
i
i
t th
h ld
TPS383xJ25
2.18
2.25
2.29
VIT
Negative-going input threshold
voltage (see Note 3)
TPS383xH30
TA = –40
°
C to 85
°
C
2.70
2.79
2.85
V
VIT
voltage (see Note 3)
TPS383xL30
TA 40 C to 85 C
2.56
2.64
2.69
V
TPS383xK33
2.84
2.93
2.99
1.7 V < VIT <
2.5 V
30
Vhys
Hysteresis at VDD input
2.5 V
<
VIT < 3.5 V
40
mV
Vhys
Hysteresis at VDD in ut
3.5 V < VIT
< 5 V
50
mV
IIH
High-level input current
MR
(see Note 4)
MR = 0.7
×
VDD,
VDD = 6 V
–40
–60
–100
µ
A
IIH
High level in ut current
CT
CT = VDD = 6 V
–25
25
nA
IIL
Low-level input current
MR
(see Note 4)
MR = 0 V,
VDD = 6 V
–130
–200
–340
µ
A
IIL
Low level in ut current
CT
CT = 0 V,
VDD = 6 V
–25
25
nA
IOH
High-level output current
TPS3838
VDD = VIT + 0.2 V,
VOH = VDD
25
nA
VDD > VIT, VDD < 3 V
220
400
nA
IDD
Supply current
VDD > VIT, VDD > 3 V
250
450
nA
IDD
Su
ly current
VDD < VIT
10
15
µ
A
Internal pullup resistor at MR
30
k
Ω
CI
Input capacitance at MR, CT
VI = 0 V to VDD
5
pF
NOTES:
2. The lowest voltage at which RESET output becomes active. tr, VDD
≥
15
µ
s/V
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1
µ
F) should be placed near the supply terminal.
4. If manual reset is unused, MR should be connected to VDD to minimize current consumption.
TPS3836E18 / J25 / H30 / L30 / K33
TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33
NANOPOWER SUPERVISORY CIRCUITS
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timing requirements at R
L
= 1 M
Ω
, C
L
= 50 pF, T
A
= 25
_
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
at VDD
VIH = VIT + 0.2 V,
VIL = VIT – 0.2 V
6
µ
s
tw
Pulse width
at MR
VDD
≥
VIT + 0.2 V,
VIL = 0.3
×
VDD,
VIH = 0.7
×
VDD
1
µ
s
switching characteristics at R
L
= 1 M
Ω
, C
L
= 50 pF, T
A
= 25
_
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
Delay time
VDD
≥
VIT + 0.2 V,
MR = 0.7
×
VDD,
CT = GND,
See timing diagram
5
10
15
ms
td
Delay time
VDD
≥
VIT + 0.2 V,
MR = 0.7
×
VDD,
CT = VDD ,
See timing diagram
100
200
300
ms
tPHL Propagation (delay) time, high-to-low-level output
VDD to RESET delay
(TPS3836 TPS3838)
VIL = VIT – 0.2 V,
VIH = VIT + 0.2 V
10
µ
s
tPHL Pro agation (delay) time, high to low level out ut
(TPS3836, TPS3838)
VIL = 1.6 V
50
µ
s
tPLH Propagation (delay) time, low-to-high-level output
VDD to RESET delay
(TPS3837)
VIL = VIT – 0.2 V,
VIH = VIT + 0.2 V
10
µ
s
tPLH Pro agation (delay) time, low to high level out ut
(TPS3837)
VIL = 1.6 V
50
µ
s
tPHL Propagation (delay) time, high-to-low-level output
MR to RESET delay
(TPS3836, TPS3838)
VDD
≥
VIT + 0.2 V,
VIL = 0.3
×
VDD,
0.1
µ
s
tPLH Propagation (delay) time, low-to-high-level output
MR to RESET delay
(TPS3837)
VIL = 0.3
×
VDD,
VIL = 0.7
×
VDD
0.1
µ
s
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
IDD
Supply current
vs Supply voltage
1
IMR
Manual reset current
vs Manual reset voltage
2
VOL
Low-level output voltage
vs Low-level output current
3
VOH
High-level output voltage
vs High-level output current
4
Normalized reset threshold voltage
vs Free-air temperature
5
Minimum pulse duration at VDD
vs VDD Threshold overdrive
6
TPS3836E18 / J25 / H30 / L30 / K33
TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33
NANOPOWER SUPERVISORY CIRCUITS
SLVS292A – JUNE 2000 – REVISED JANUARY 2002
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TYPICAL CHARACTERISTICS
0
2
4
6
8
10
0
2
4
6
Figure 1
VDD – Supply Voltage – V
MR = Open
CT = GND
I DD
–
Supply Current
–
µ
A
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
TA = –40
°
C
TA = 0
°
C
TA = 25
°
C
TA = 85
°
C
Figure 2
VMR – Manual Reset Voltage – V
–500
–400
–300
–200
–100
0
100
–2
0
2
4
6
I MR
–
Manual Reset Current
–
µ
A
MANUAL RESET CURRENT
vs
MANUAL RESET VOLTAGE
VDD = 6 V
CT = GND
TA = 25
°
C
TA = 85
°
C
TA = 0
°
C
TA = –40
°
C
Figure 3
IOL – Low-Level Output Current – mA
0.0
0.5
1.0
1.5
2.0
0
1
2
3
4
5
6
7
VDD = 2 V
MR = OPEN
CT = GND
V
OL
–
Low-Level Output V
oltage
–
V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
TA = 25
°
C
TA = –40
°
C
TA = 85
°
C
TA = 0
°
C
Figure 4
0.0
0.5
1.0
1.5
2.0
0
1
2
3
4
5
IOH – High-Level Output Current – mA
V
OH
–
High-Level Output V
oltage
–
V
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VDD = 2 V
MR = OPEN
CT = GND
TA = 85
°
C
TA = –40
°
C
TA = 0
°
C
TA = 25
°
C
TPS3836E18 / J25 / H30 / L30 / K33
TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33
NANOPOWER SUPERVISORY CIRCUITS
SLVS292A – JUNE 2000 – REVISED JANUARY 2002
9
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•
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TYPICAL CHARACTERISTICS
Figure 5
0.995
0.996
0.997
0.998
0.999
1.001
–40
–15
10
35
60
85
Normalized Reset Threshold V
oltage
–
V
NORMALIZED RESET THRESHOLD
VOLTAGE
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature –
°
C
CT = GND,
MR = Open
1
0
2
4
6
8
10
12
14
16
18
20
22
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
MINIMUM PULSE DURATION AT V
DD
vs
V
DD
THRESHOLD OVERDRIVE
MR = Open
CT = GND
TA = 25
°
C
VDD – Threshold Overdrive – V
Minimum Pulse Duration at V
DD
–
µ
s
Figure 6
TPS3836E18 / J25 / H30 / L30 / K33
TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33
NANOPOWER SUPERVISORY CIRCUITS
SLVS292A – JUNE 2000 – REVISED JANUARY 2002
10
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•
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MECHANICAL DATA
DBV (R-PDSO-G5)
PLASTIC SMALL-OUTLINE
0,10
M
0,20
0,95
0
°
–8
°
0,25
0,35
0,55
Gage Plane
0,15 NOM
4073253-4/E 05/99
2,60
3,00
0,50
0,30
1,50
1,70
4
5
3
1
2,80
3,00
0,95
1,45
0,05 MIN
Seating Plane
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-178
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accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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