Publication# 14051
Rev: K
Amendment/0
Issue Date: November 1998
MACH 1 and 2 CPLD Families
High-Performance EE CMOS Programmable Logic
FEATURES
x
High-performance electrically-erasable CMOS PLD families
x
32 to 128 macrocells
x
44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages
x
SpeedLocking™ – guaranteed fixed timing up to 16 product terms
x
Commercial 5/5.5/6/7.5/10/12/15-ns t
PD
and Industrial 7.5/10/12/14/18-ns t
PD
x
Configurable macrocells
— Programmable polarity
— Registered or combinatorial outputs
— Internal and I/O feedback paths
— D-type or T-type flip-flops
— Output Enables
— Choice of clocks for each flip-flop
— Input registers for MACH 2 family
x
JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available
x
Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.5/10/12 ns
x
Safe for mixed supply voltage system designs
x
Bus-Friendly™ inputs and I/Os reduce risk of unwanted oscillatory outputs
x
Programmable power-down mode results in power savings of up to 75%
x
Supported by Vantis DesignDirect™ software for rapid logic development
— Supports HDL design methodologies with results optimized for Vantis
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
x
Lattice/Vantis and third-party hardware programming support
— Lattice/VantisPRO™ (formerly known as MACHPRO
®
) software for in-system programmability
support on PCs and Automated Test Equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
2
MACH 1 & 2 Families
Note:
1. Values in parentheses ( ) are for the SP version.
GENERAL DESCRIPTION
The MACH
®
1 & 2 families from Lattice/Vantis offer high-performance, low cost Complex
Programmable Logic Devices (CPLDs), addressing the growing need for speed in networking,
telecommunications and computing. MACH 1 & 2 devices are available in speeds as fast as 5.0-ns
t
PD
and in densities ranging from 32 to 128 macrocells (Tables 1 and 2). The overall benefits for
users include guaranteed high performance for entry-to-mid-level logic needs at a low cost.
Notes:
1. C = Commercial, I = Industrial
2. -5 speed grade for MACH111 (SP) = 5.0 ns t
PD
3. -5 speed grade for MACH131(SP) = 5.5 ns t
PD
The MACH 1 & 2 families consist of ten devices—five base options, each with a counterpart that
includes JTAG-compatible in-system programming (ISP). These devices offer five different density-
I/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), and Plastic
PCI compliant and includes other features such as SpeedLocking architecture for guaranteed fixed
timing, Bus-Friendly inputs and I/Os, and programmable power-down mode for extra power
savings.
Table 1. MACH 1 and 2 Family Device Features
1
Feature
MACH111 (SP)
MACH131 (SP)
MACH211 (SP)
MACH221 (SP)
MACH231 (SP)
Macrocells
32
64
64
96
128
Maximum user I/O pins
32
64
32
48
64
t
P D
(ns)
5.0
5.5
7.5 (6.0)
7.5
6.0 (10)
t
S
(ns)
3.5
3.0
5.5 (5)
5.5
5 (6.5)
t
CO
(ns)
3.5
4
4.5 (4)
5
4 (6.5)
f
CNT
(MHz)
182
182
133 (166)
133
166 (100)
Table 2. MACH 1 and 2 Family Speed Grades
1
Device
-5
-6
-7
-10
-12
-14
-15
-18
MACH111
C (Note 2)
C, I
C, I
C, I
I
C
I
MACH111SP
C (Note 2)
C, I
C, I
C, I
I
C
I
MACH131
C (Note 3)
C, I
C, I
C, I
I
C
I
MACH131SP
C (Note 3)
C, I
C, I
C, I
I
C
I
MACH211
C
C, I
C, I
I
C
I
MACH211SP
C
C
C, I
C, I
I
C
I
MACH221
C
C, I
C, I
I
C
I
MACH221SP
C
C, I
C, I
I
C
I
MACH231
C
C
C
C, I
I
C
I
MACH231SP
C
C, I
I
C
I
MACH 1 & 2 Families
3
Note:
1. The MACH110, MACH120, MACH130, MACH210, MACHLV210, MACH215, MACH220 and MACH230 are not listed above and
not recommended for new designs. However, they are still supported by Lattice/Vantis. For technical or sales support, please call
your local Lattice/Vantis sales office or visit our Web site at www.vantis.com for more information.
Lattice/Vantis offers software design support for MACH devices in both the MACHXL
®
and
DesignDirect development systems. The DesignDirect development system is the Lattice/Vantis
implementation software that includes support for all Lattice/Vantis CPLD, FPGA, and SPLD
devices. This system is supported under Windows ’95, ’98 and NT as well as Sun Solaris and HPUX.
DesignDirect software is designed for use with design entry, simulation and verification software
from leading-edge tool vendors such as Cadence, Exemplar Logic, Mentor Graphics, Model
Technology, Synopsys, Synplicity, Viewlogic and others. It accepts EDIF 2 0 0 input netlists,
generates JEDEC files for Lattice/Vantis PLDs and creates industry-standard EDIF, Verilog, VITAL
compliant VHDL and SDF simulation netlists for design verification.
DesignDirect software is also available in product configurations that include VHDL and Verilog
synthesis from Exemplar Logic and VHDL, Verilog RTL and gate level timing simulation from Model
Technology. Schematic capture and ABEL entry, as well as functional simulation, are also provided.
Table 3. MACH 1 and 2 Family Package and I/O Options
Device
44-pin PLCC
44-pin TQFP
68-pin PLCC
84-pin PLCC
100-pin TQFP
100-pin PQFP
MACH111
X
X
MACH111SP
X
X
MACH131
X
MACH131SP
X
X
MACH211
X
X
MACH211SP
X
X
MACH221
X
MACH221SP
X
MACH231
X
MACH231SP
X
X
4
MACH 1 & 2 Families
FUNCTIONAL DESCRIPTION
Each MACH 1 and 2 device consists of multiple, optimized PAL
®
blocks interconnected by a switch
matrix. The switch matrix allows communication between PAL blocks, and routes inputs to the PAL
blocks. Together, the PAL blocks and switch matrix allow the logic designer to create large designs
in a single device instead of using multiple devices.
The switch matrix takes all dedicated inputs and signals from the input switch matrices and routes
them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must
go through the switch matrix. This mechanism ensures that PAL blocks in MACH devices
communicate with each other with guaranteed fixed timing (SpeedLocking).
The switch matrix makes a MACH device more advanced than simply several PAL devices on a
single chip. It allows the designer to think of the device not as a collection of blocks, but as a
single programmable device; the software partitions the design into PAL blocks through the
central switch matrix so that the designer does not have to be concerned with the internal
architecture of the device.
14051K-002
Figure 1. Overall Architecture of MACH 1 & 2 Devices
Array and
Allocator
Output
Macrocells
Buried
Macrocells
I/O Cells
Buried Macrocell Feedback
Output Macrocell Feedback
I/O Pin Feedback
I/O Pins
Switch Matrix
PAL Block
I/O Pins
PAL Block
PAL Block
Clock/Input Pins
Dedicated Input
Note:
1. There are no buried macrocells in MACH 1 devices. All macrocells are output macrocells.
PAL Block
Device
PAL Blocks
Macrocells per Block
I/Os per Block
Product Terms per Block
MACH111(SP)
2
16
16
70
MACH131(SP)
4
16
16
70
MACH211(SP)
4
16
8
68
MACH221(SP)
8
12
6
52
MACH231(SP)
8
16
8
68
(note 1)
I/O Pins
I/O Pins
MACH 1 & 2 Families
5
Each PAL block consists of the following elements:
x
Product-term array
x
Logic Allocator
x
Macrocells
x
I/O cells
Each PAL block additionally contains an asynchronous reset product term and an asynchronous
preset product term. This allows the flip-flops within a single PAL block to be initialized as a bank.
There are also output enable product terms that provide tri-state control for the I/O cells.
Product-Term Array
The product-term array consists of a number of product terms that form the basis of the logic being
implemented. The inputs to the AND gates come from the switch matrix (Table 4), and are
provided in both true and complement forms for efficient logic implementation.
Because the number of product terms available for a given function is not fixed, the full sum of
products is not realized in the array. The product terms drive the logic allocator, which allocates
the appropriate number of product terms to generate the function.
Logic Allocator
appropriate macrocells in groups of four product terms called “product term clusters”. The
availability and distribution of product term clusters is automatically considered by the software as
it fits functions within the PAL block. The size of the product term clusters has been designed to
provide high utilization of product terms. Complex functions using many product terms are
possible, and when few product terms are used, there will be a minimal number of unused, or
wasted, product terms left over.
The product term clusters do not “wrap” around the logic block. This means that the macrocells
at the ends of the block have fewer product terms available (Tables 5, 6, 7, 8).
Table 4. PAL Block Inputs
Device
Number of Inputs to PAL Block
Device
Number of Inputs to PAL Block
MACH111
26
MACH211SP
26
MACH111SP
26
MACH221
26
MACH131
26
MACH221SP
26
MACH131SP
26
MACH231
32
MACH211
26
MACH231SP
32
6
MACH 1 & 2 Families
Table 5. Logic Allocation for MACH111(SP)
Output Macrocell
Available Clusters
Output Macrocell
Available Clusters
M
0
C
0
, C
1
M
8
C
8,
C
9
M
1
C
0
, C
1
, C
2
M
9
C
8,
C
9,
C
10
M
2
C
1
, C
2
, C
3
M
10
C
9,
C
10,
C
11
M
3
C
2
, C
3
, C
4
M
11
C
10,
C
11,
C
12
M
4
C
3
, C
4
, C
5
M
12
C
11,
C
12,
C
13
M
5
C
4
, C
5
, C
6
M
13
C
12,
C
13,
C
14
M
6
C
5
, C
6
, C
7
M
14
C
13,
C
14,
C
15
M
7
C
6
, C
7
M
15
C
14,
C
15
Table 6. Logic Allocation for MACH131(SP)
Output Macrocell
Available Clusters
Output Macrocell
Available Clusters
M
0
C
0
, C
1
M
8
C
7
, C
8
, C
9
M
1
C
0
, C
1
, C
2
M
9
C
8
, C
9
, C
10
M
2
C
1
, C
2
, C
3
M
10
C
9
, C
10
, C
11
M
3
C
2
, C
3
, C
4
M
11
C
10
, C
11
, C
12
M
4
C
3
, C
4
, C
5
M
12
C
11
, C
12
, C
13
M
5
C
4
, C
5
, C
6
M
13
C
12
, C
13
, C
14
M
6
C
5
, C
6
, C
7
M
14
C
13
, C
14
, C
15
M
7
C
6
, C
7
, C
8
M
15
C
14
, C
15
*
*
*MACH 2 only
Product Term
Cluster
Logic
Allocator
From
n+1
From
n+2
From
n-1
To
n-2
To
n-1
n
To
n+1
n
To Macrocell
n
Figure 2. Product Term Clusters and the Logic Allocator
14051K-003
MACH 1 & 2 Families
7
Macrocell
There are two fundamental types of macrocell: the output macrocell and the buried macrocell. The
buried macrocell is only found in MACH 2 devices. The use of buried macrocells effectively
doubles the number of macrocells available without increasing the pin count.
Both macrocell types can generate registered or combinatorial outputs. For the MACH 2 series,
a transparent-low latch configuration is provided. If the register is used, it can be configured as
a T-type or a D-type flip-flop. Register and latch functionality is defined in Table 9.
Programmable polarity (for output macrocells) and the T-type flip-flop both give the software a
way to minimize the number of product terms needed. These choices can be made automatically
by the software when it fits the design into the device.
Table 7. Logic Allocation for MACH211(SP) and MACH231(SP)
Macrocell
Available Clusters
Macrocell
Available Clusters
Output
Buried
Output
Buried
M
0
M
1
C
0
, C
1
, C
2
C
0
, C
1
, C
2
, C
3
M
8
M
9
C
7
, C
8
, C
9
, C
10
C
8
, C
9
, C
10
, C
11
M
2
M
3
C
1
, C
2
, C
3
, C
4
C
2
, C
3
, C
4
, C
5
M
10
M
11
C
9
, C
10
, C
11
, C
12
C
10
, C
11
, C
12
, C
13
M
4
M
5
C
3
, C
4
, C
5
, C
6
C
4
, C
5
, C
6
, C
7
M
12
M
13
C
11
, C
12
, C
13
, C
14
C
12
, C
13
, C
14
, C
15
M
6
M
7
C
5
, C
6
, C
7
, C
8
C
6
, C
7
, C
8
, C
9
M
14
M
15
C
13
, C
14
, C
15
C
14
, C
15
Table 8. Logic Allocation for MACH221(SP)
Macrocell
Available Clusters
Macrocell
Available Clusters
Output
Buried
Output
Buried
M
0
M
1
C
0
, C
1
, C
2
C
0
, C
1
, C
2
, C
3
M
6
M
7
C
5
, C
6
, C
7
, C
8
C