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START

STOP

LOGIC

CONTROL

LOGIC

SLAVE

ADDRESS

REGISTER

&

COMPARATOR

WORD

ADDRESS

COUNTER

H.V.

GENERATION

TIMING

&

CONTROL

XDEC

EEPROM

ARRAY

DATA

BIT

64X4X8

YDEC

DATA

REGISTER

DOUT

ACK

SDA

SCL

A0

A1

A2

VCC

VSS

Din

R/W ~

2

8

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4

64

6

inc

load

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start cycle

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Figure 3. Acknowledge Response from Receiver

8

1

9

ACKNOWLEDGE

START

SCL FROM MASTER

DATA OUTPUT FROM

TRANSMITTER

DATA OUTPUT FROM

RECEIVER

SCL

Figure 1. Data Validity

SDA

IN

Tf

Thd:Sta

Thd:Dat

Tsu:Dat

Tbuf

Tlow

Thigh

Tlow

Tr

Tsu:Sta

Tsu:Sta

SDA

OUT

Tdh

Taa

DATA STABLE

DATA

CHANGE

SDA

SCL

Figure 2. Definition of Start and Stop

BIT

STOP

START

BIT

SDA

SCL

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ATC

DATA

P

A

C

K

Figure 6. Current Address Read for Data

s

BUS ACTIVITY

SLAVE

SDA

LINE

BUS ACTIVITY

MASTER

SLAVE

ADDRESS

STOP

START

S

A

C

K

DATA n

A

C

K

DATA n+1

A

C

K

DATA n+x

P

Figure 8. Sequential Read for Data

BUS ACTIVITY

SLAVE

SDA

LINE

BUS ACTIVITY

MASTER

SLAVE

ADDRESS

START

STOP

P

S

S

A

C

K

A

C

K

A

C

K

DATA n

Figure 7. Random Read for Data

BYTE

ADDRESS n

SLAVE

ADDRESS

STOP

START

SLAVE

ADDRESS

START

BUS ACTIVITY

SLAVE

SDA

LINE

BUS ACTIVITY

MASTER

Figure 5. Page Write for Data

BUS ACTIVITY

SLAVE

SDA

LINE

BUS ACTIVITY

MASTER

DATA n

BYTE

ADDRESS n

SLAVE

ADDRESS

STOP

START

DATA n+7

A

C

K

A

C

K

A

C

K

A

C

K

S

P

DATA n

BYTE

ADDRESS

SLAVE

ADDRESS

A

C

K

A

C

K

A

C

K

BUS ACTIVITY

SLAVE

SDA

LINE

BUS ACTIVITY

MASTER

Figure 4. Byte Write for Data

S

P

STOP

START

No

A

C

K

A

C

K

No

A

C

K

No

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7

15 (4X)

(4X)

E1

D

PIN #1 INDENT O0.025 DEEP 0.006-0.008

E-PIN O0.118 NOTE 9

A

L

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A1

B2

B1

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VIEW "A"

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A

E

E1

b

y

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C

DETAIL A

DETAIL A

L 1

L

E1

L1

A2

A1

D

PIN 1 INDICATOR O0.70

SURFACE POLISHED