A67L83161_A67L83181

A67L83161/A67L83181/

A67L73321/A67L73361 Series

256K X 16/18, 128K X 32/36

Preliminary

LVTTL, Flow-through DBA

SRAM

PRELIMINARY (September, 1999, Version 0.1)

AMIC Technology, Inc.

DBA and Direct Bus Alternation are trademarks of AMIC Technology, Inc

Document Title

256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBA

SRAM

Revision History

Rev.

No.

History

Issue Date

Remark

0.0

Initial issue

April 7, 1999

Preliminary

0.1

Change fast access time from 7.5/8.0/8.5/9.0 ns to 10/11/12

September 15, 1999

Change set-up time from 2.0/2.2/2.5 ns to 2.5 ns

Fix pin assignment error for pin 14 and pin 16

A67L83161/A67L83181/

A67L73321/A67L73361 Series

256K X 16/18, 128K X 32/36

Preliminary

LVTTL, Flow-through DBA

SRAM

PRELIMINARY (September, 1999, Version 0.1)

AMIC Technology, Inc.

DBA and Direct Bus Alternation are trademarks of AMIC Technology, Inc

Features

Fast access time: 10/11/12 ns

(100, 90, 83 MHz)

Direct Bus Alternation between READ and WRITE

cycles allows 100% bus utilization

Signal +3.3V

5% power supply

Individual Byte Write control capability

Clock enable (

CEN

) pin to enable clock and suspend

operations

Clock-controlled and registered address, data and

control signals

Registered output for pipelined applications

Three separate chip enables allow wide range of

options for CE control, address pipelining

Internally self-timed write cycle

Selectable BURST mode (Linear or Interleaved)

SLEEP mode (ZZ pin) provided

Available in 100 pin LQFP package

General Description

The AMIC Direct Bus Alternation™ (DBA™) SRAM

family employs high-speed, low-power CMOS designs

using an advanced CMOS process.

The A67L83161, A67L83181, A67L73321, A67L73361

SRAMs integrate a 256K X 16, 256K X 18, 128K X 32 or

128K X 36 SRAM core with advanced synchronous

peripheral circuitry and a 2-bit burst counter. These

SRAMs are optimized for 100 percent bus utilization

without the insertion of any wait cycles during Write-

Read alternation. The positive edge triggered single

clock input (CLK) controls all synchronous inputs

passing through the registers. The synchronous inputs

include all address, all data inputs, active low chip

enable (

), two additional chip enables for easy depth

expansion (CE2,

CE2

), cycle start input (ADV/LD ),

synchronous clock enable (

CEN

), byte write enables

(

BW1

BW2

BW3

BW4

) and read/write (R/

Asynchronous inputs include the output enable (

clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and

burst mode (MODE). Burst Mode can provide either

interleaved or linear operation, burst operation can be

initiated by synchronous address Advance/Load

(ADV/LD ) pin in Low state. Subsequent burst address

can be internally generated by the chip and controlled by

the same input pin ADV/LD in High state.

Write cycles are internally self-time and synchronous

with the rising edge of the clock input and when R/

Low. The feature simplified the write interface. Individual

Byte enables allow individual bytes to be written.

BW1

controls I/Oa pins;

BW2

controls I/Ob pins;

BW3

controls I/Oc pins; and

BW4

controls I/Od pins. Cycle

types can only be defined when an address is loaded,

i.e., when ADV/LD is LOW. Parity/ECC bits are only

available on the X18/36 version.

The SRAM operates from a +3.3V power supply, and all

inputs and outputs are LVTTL-compatible. The device is

ideally suited for high bandwidth utilization systems.

A67L83161/A67L83181/

A67L73321/A67L73361 Series

PRELIMINARY (September, 1999, Version 0.1)

AMIC Technology, Inc.

Pin Configuration

A16

A15

A14

A13

A12

A11

A10

VCC

VSS

MODE

100

256K X 18/16

A16

A15

A14

A13

A12

A11

A10

VCC

VSS

MODE

128K X 36/32

I/Ob

/NC

I/Oa

CE2

VCC

VSS

CLK

A17

VCCQ

VSSQ

VCCQ

VSS

VCC

VCCQ

VSSQ

VCCQ

I/Oa

/NC

I/Oa

VCCQ

VSSQ

VCCQ

VSS

VCC

VSS

VCCQ

VSSQ

VCCQ

I/Ob

VCC

I/Ob

CE2

CLK

VSS

VCC

VCCQ

VSSQ

VCCQ

VSS

VCC

VCCQ

VSSQ

VCCQ

I/Ob

BW4

BW3

BW2

BW1

CE2

CEN

ADV/

A67L83161E

A67L83181E

A67L73321E

A67L73361E

R/W

I/Ob

/NC

VCCQ

VSSQ

VCCQ

VCC

VSS

VCCQ

VSSQ

VCCQ

VSS

I/Oc

/NC

I/Oc

I/Od

/NC

I/Oa

I/Ob

I/Oa

A67L83161/A67L83181/

A67L73321/A67L73361 Series

PRELIMINARY (September, 1999, Version 0.1)

AMIC Technology, Inc.

Block Diagram (128K X 32/36)

MODE

LOGIC

CLK

LOGIC

ADDRESS

REGISTERS

BURST

LOGIC

ADDRESS

COUNTER

CLR

WRITE

REGISTRY

CONTROL

LOGIC

BYTEa

WRITE

DRIVER

BYTEb

WRITE

DRIVER

BYTEc

WRITE

DRIVER

BYTEd

WRITE

DRIVER

8/9

128KX8/X9X4

MEMORY

ARRAY

8/9

OUTPUT

BUFFERS

CHIP

ENABLE

LOGIC

PIPELINED

ENABLE

LOGIC

OUTPUT

ENABLE

LOGIC

MODE

ADV/LD

CLK

A0-A16

R/W

BWE

BW1

BW2

BW3

BW4

CE2

CEN

WRITE

ADDRESS

ADV/LD

DATA-IN

REGISTERS

I/O

SENSE

AMPS

A67L83161/A67L83181/

A67L73321/A67L73361 Series

PRELIMINARY (September, 1999, Version 0.1)

AMIC Technology, Inc.

Block Diagram (256K X 16/18)

DATA-IN

REGISTERS

MODE

LOGIC

CLK

LOGIC

ADDRESS

REGISTERS

BURST

LOGIC

ADDRESS

COUNTER

CLR

WRITE

REGISTRY

CONTROL

LOGIC

BYTEa

WRITE

DRIVER

BYTEb

WRITE

DRIVER

8/9

256KX8/X9X2

MEMORY

ARRAY

8/9

OUTPUT

BUFFERS

CHIP

ENABLE

LOGIC

PIPELINED

ENABLE

LOGIC

OUTPUT

ENABLE

LOGIC

MODE

ADV/LD

CLK

A0-A17

R/W

BWE

BW1

BW2

CE2

CEN

WRITE

ADDRESS

ADV/LD

I/O

SENSE

AMPS

A67L83161/A67L83181/

A67L73321/A67L73361 Series

PRELIMINARY (September, 1999, Version 0.1)

AMIC Technology, Inc.

Pin Description

Pin No.

Symbol

Description

LQFP (X16/X18)

LQFP (X32/X36)

35,34,33,32,

100,99,82,81,

44,45,46,47,

48,49,50

35,34,33,32,

100,99,82,81,

44,45,46,47,

48,49,50

A2 - A16

A17

Synchronous Address Inputs : These inputs are registered

and must meet the setup and hold times around the rising

edge of CLK. Pins 83 and 84 are reserved as address bits

for higher-density 9Mb and 18Mb DBA SRAMs, respectively.

A0 and A1 are the two lest significant bits (LSB) of the

address field and set the internal burst counter if burst is

desired.

93 (

BW1

)

94 (

BW2

)

93 (

BW1

)

94 (

BW2

)

95 (

BW3

)

96 (

BW4

)

BW1

BW2

BW3

BW4

Synchronous Byte Write Enables : These active low inputs

allow individual bytes to be written when a WRITE cycle is

active and must meet the setup and hold times around the

rising edge of CLK. BYTE WRITEs need to be asserted on

the same cycle as the address,

BWs

are associated with

addresses and apply to subsequent data.

BW1

controls I/Oa

pins;

BW2

controls I/Ob pins;

BW3

controls I/Oc pins;

BW4

controls I/Od pins.

CLK

Clock : This signal registers the address, data, chip

enables, byte write enables and burst control inputs on its

rising edge. All synchronous inputs must meet setup and

hold times around the clock’s rising edge.

Synchronous Chip Enable : This active low input is used to

enable the device. This input is sampled only when a new

external address is loaded (ADV/LD LOW).

CE2

Synchronous Chip Enable : This active low input is used to

enable the device and is sampled only when a new external

address is loaded (ADV/LD LOW). This input can be used

for memory depth expansion.

CE2

Synchronous Chip Enable : This active high input is used to

enable the device and is sampled only when a new external

address is loaded (ADV/LD LOW). This input can be used

for memory depth expansion.

Output Enable : This active low asynchronous input enables

the data I/O output drivers.

ADV/LD

Synchronous Address Advance/Load : When HIGH, this

input is used to advance the internal burst counter,

controlling burst access after the external address is loaded.

When HIGH, R/

is ignored. A LOW on this pin permits a

new address to be loaded at CLK rising edge.

A67L83161/A67L83181/

A67L73321/A67L73361 Series

PRELIMINARY (September, 1999, Version 0.1)

AMIC Technology, Inc.

Pin Description (continued)

Pin No.

Symbol

Description

LQFP (X16/X18)

LQFP (X32/X36)

CEN

Synchronous Clock Enable : This active low input permits

CLK to propagate throughout the device. When HIGH, the

device ignores the CLK input and effectively internally

extends the previous CLK cycle. This input must meet setup

and hold times around the rising edge of CLK.

Snooze Enable : This active high asynchronous input

causes the device to enter a low-power standby mode in

which all data in the memory array is retained. When active,

all other inputs are ignored.

Read/Write : This active input determines the cycle type

when ADV/LD is LOW. This is the only means for

determining READs and WRITEs. READ cycles may not be

converted into WRITEs (and vice versa) other than by

loading a new address. A LOW on this pin permits BYTE

WRITE operations and must meet the setup and hold times

around the rising edge of CLK. Full bus width WRITEs

occur if all byte write enables are LOW.

(a) 58, 59, 62, 63,

68, 69, 72, 73

(b) 8,9,12,13, 18,

19, 22,23

(a) 52, 53, 56, 57,

58, 59, 62, 63

(b) 68, 69, 72, 73,

74, 75, 78, 79

12, 13,

(d) 18, 19, 22, 23,

24, 25, 28, 29

I/Oa

I/Ob

I/Oc

I/Od

SRAM Data I/O : Byte “a” is I/Oa pins; Byte “b” is I/Ob pins;

Byte “c” is I/Oc pins; Byte “d” is I/Od pins. Input data must

meet setup and hold times around CLK rising edge.

NC/I/Oa

NC/I/Ob

NC/I/Oc

NC/I/Od

No Connect/Data Bits : On the X16/32 version, these pins

are no connect (NC) and can be left floating or connected to

GND to minimize thermal impedance. On the X18/36

version, these bits are I/Os.

MODE

Mode : This input selects the burst sequence. A LOW on

this pin selects linear burst. NC or HIGH on this pin selects

interleaved burst. Do not alter input state while device is

operating.

1, 2, 3, 6, 7, 25,

28, 29, 30, 38, 39,

42, 43, 51, 52, 53,

56, 57, 75, 78, 79,

83, 84, 95, 96

38,39,42,43

83,84

No Connect : These pins can be left floating or connected to

GND to minimize thermal impedance.

A67L83161/A67L83181/

A67L73321/A67L73361 Series

PRELIMINARY (September, 1999, Version 0.1)

AMIC Technology, Inc.

Truth Table (Notes 5 - 7)

Operation

Address

Used

CE2

ADV/

BWx OE

CEN

CLK

I/O

Notes

Deselected Cycle,

Power-down

None

→

High-Z

Deselected Cycle,

Power-down

None

→

High-Z

Deselected Cycle,

Power-down

None

→

High-Z

Continue Deselect

Cycle

None

→

High-Z

READ Cycle

(Begin Burst)

External

→

READ Cycle

(Continue Burst)

→

1,7

NOP/Dummy READ

(Begin Burst)

External

→

High-Z

Dummy READ

(Continue Burst)

→

High-Z

1,2,7

WRITE Cycle

(Begin Burst)

External

→

WRITE Cycle

(Continue Burst)

→

1,3,7

NOP/WRITE Abort

(Begin Burst)

None

→

High-Z

2,3

WRITE Abort

(Continue Burst)

→

High-Z

1,2,3,7

IGNORE Clock

Edge

(Stall)

Current

→

SLEEP Mode

None

High-Z

Notes:

1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or

WRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is

executed first.

2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITE

Abort means a WRITE command is given, but no operation is performed.

3. OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off

the output drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not

meet their requirements.

4. If an Ignore Clock Edge command occurs during a READ operation, the I/O bus will remain active (Low-Z). If it occurs

during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock

Edge cycle.

5. X means “Don’t Care.” H means logic HIGH. L means logic LOW.

BWx

= H means all byte write signals

(

BW1

BW2

BW3

and

BW4

) are HIGH.

BWx

= L means one or more byte write signals are LOW.

BW1

enables WRITEs to Byte “a” (I/Oa pins);

BW2

enables WRITEs to Byte “b” (I/Ob pins);

BW3

enables WRITEs to

Byte “c” (I/Oc pins);

BW4

enables WRITEs to Byte “d” (I/Od pins).

7. The address counter is incremented for all Continue Burst cycles.