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A62L256 Series

Preliminary

32K X 8 BIT LOW VOLTAGE CMOS SRAM

PRELIMINARY (November, 2001, Version 1.4)

AMIC Technology, Inc.

Document Title

32K X 8 BIT LOW VOLTAGE CMOS SRAM

Revision History

Rev. No. History

Issue Date

Remark

1.0

Initial issue

September 01, 1997

1.1

Modify 28-pin DIP, SOP and TSOP packages outline

January 20, 1998

dimensions.

1.2

Modify 28-pin SOP and TSOP packages outline drawings

June 17, 1998

and dimensions

1.3

Add -LLU type

April 11, 2001

Change operating voltage Vccmax from 3.3V to 3.6V

1.4

Add Product Family in page 1

November 30, 2001

Delete I

item

Add I

CC2

(typ.) I

CCDR

(typ.)

Change I

SB1

(typ.) I

CCDR

(max.)

Change ordering information from I

CC1

to I

CC2

A62L256 Series

Preliminary

32K X 8 BIT LOW VOLTAGE CMOS SRAM

PRELIMINARY (November, 2001, Version 1.4)

AMIC Technology, Inc.

Features

External Operating Voltage: 2.7V to 3.6V

Access times: 55ns (max.): for VCC = 3.0V to 3.6V

70ns (max.): for VCC = 2.7V to 3.6V

Current: Operating (I

CC1

): -55 series 18mA (typ.)

-70 series 12mA (typ.)

Standby (I

SB1

): 0.05

A (typ.)

Extended operating temperature range: -40º C to

+85º C for -LLU series

Full static operation, no clock or refreshing required

All inputs and outputs are directly TTL-compatible

Common I/O using three-state output

Data retention voltage: 2.0V (min.)

Available in 28-pin DIP, SOP and TSOP (forward and

reverse type) packages

General Description

The A62L256 is a low operating current 262,144-bit static

random access memory organized as 32,768 words by 8

bits and operates on a low power voltage: 2.7V to 3.6V.

Inputs and three-state outputs are TTL compatible and

allow for direct interfacing with common system bus

structures.

Minimum standby power is drawn by this device when

CE is at a high level, independent of the other input

levels.

Data retention is guaranteed at a power supply voltage

as low as 2.0V.

Product Family

Power Dissipation

Product Family

Operating

Temperature

VCC

Range

Speed

Data Retention

CCDR

, Typ.)

Standby

SB1

, Typ.)

Operating

CC2

, Typ.)

Package

Type

A62L256

-40

C ~ +85

C 2.7V~3.6V

55ns / 70ns

0.02

0.05

1mA

28L DIP

28L SOP

28L TSOP

1. Typical values are measured at VCC = 3.0V, T

= 25

C and not 100% tested.

2. Data retention current VCC = 2.0V.

Pin Configurations

DIP

SOP

TSOP

A14

A12

I/O

GND

I/O

A11

A13

VCC

A10

A62L256

A14

A12

I/O

GND

I/O

A11

A13

VCC

A10

A62L256M

A62L256V

A11

A13

A14

A12

I/O

VSS

I/O

A10

VCC

I/O

A62L256R

VCC

A13

A11

I/O

VSS

I/O

A10

A14

A12

A62L256 Series

PRELIMINARY (November, 2001, Version 1.4)

AMIC Technology, Inc.

Block Diagram

ROW

DECODER

512 X 512

MEMORY ARRAY

COLUMN I/O

COLUMN DECODER

INPUT

DATA

CIRCUIT

CONTORL

CIRCUIT

VCC

GND

A10

I/O

A14

A11

Pin Descriptions - DIP/SOP

Pin No.

Symbol

Description

1-10, 21, 23-26

A0 - A14

Address Input

11-13, 15-19

I/O

- I/O

Data Input/Output

GND

Ground

Chip Enable

Output Enable

Write Enable

VCC

Power Supply

Pin Description-TSOP

Pin No.

Symbol

Description

Output Enable

2-5, 8-17, 28

A0 - A14

Address Input

VCC

Power Supply

Write Enable

18-20, 22-26

I/O

- I/O

Data Input/Output

GND

Ground

Chip Enable

A62L256 Series

PRELIMINARY (November, 2001, Version 1.4)

AMIC Technology, Inc.

Recommended DC Operating Conditions

= 0

C to + 70

C or -40

C to +85

Symbol

Parameter

Min.

Typ.

Max.

Unit

VCC

Supply Voltage

2.7

3.0

3.6

GND

Ground

Input High Voltage

VCC * 0.7

VCC + 0.3

Input Low Voltage

-0.3

+0.3

Absolute Maximum Ratings*

VCC to GND . . . . . . . . . . . . . . . . . . . . . -0.5V to +3.6V

IN, IN/OUT Volt to GND . . . . . . . . . -0.5V to VCC + 0.5V

Operating Temperature, Topr . . . . . . . . . . 0

C to +70

Storage Temperature, Tstg . . . . . . . . . -55

C to +125

Power Dissipation, P

. . . . . . . . . . . . . . . . . . . . . 0.7W

Soldering Temp. & Time . . . . . . . . . . . . . 260

C, 10 sec

*Comments

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device.

These are stress ratings only. Functional operation of this

device at these or any other conditions above those

indicated in the operational sections of this specification

is not implied and exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

DC Electrical Characteristics

= 0

C to + 70

C or -40º C to +85º C, VCC = 2.7V to 3.6V, GND = 0V)

Symbol

Parameter

A62L256-55LL/55LLU

A62L256-70LL/70LLU

Unit

Conditions

Min.

Typ.

Max.

Min.

Typ.

Max.



Input Leakage

Current

= GND to VCC



Output Leakage

Current

CE = V

or WE = V

I/O

= GND to VCC

CC1

Dynamic

Operating Current

*18

**12

Min. Cycle, Duty = 100%

CE = V

, I

I/O

= 0mA

CC2

Dynamic

Operating Current

CE = V

, V

= VCC

= 0V, f = 1 MHz

I/O

= 0 mA

Typical values are measured at VCC = 3.0V, T

= 25

C and not 100% tested.

* Testing condition : T

= 25

C, VCC = 3.0V, Cycle Time = 55 ns

** Testing condition : T

= 25

C, VCC = 3.0V, Cycle Time = 70 ns

A62L256 Series

PRELIMINARY (November, 2001, Version 1.4)

AMIC Technology, Inc.

DC Electrical Characteristics (continued)

Symbol

Parameter

A62L256-55LL/70LL

A62L256-55LLU/70LLU

Unit

Conditions

Min.

Typ.

Max.

Min.

Typ.

Max.

Supply Current

CE = V

SB1

Standby Power

0.05

≥

VCC - 0.2V

≥

Output Low

Voltage

0.3

= 2.1mA

Output High

Voltage

VCC - 0.3

= -1.0mA

Typical values are measured at VCC = 3.0V, T

= 25

C and not 100% tested.

Truth Table

Mode

I/O Operation

Supply Current

Standby

High Z

, I

SB1

Output Disable

High Z

, I

CC1

, I

CC2

Read

OUT

, I

CC1

, I

CC2

Write

, I

CC1

, I

CC2

Note: X: H or L

Capacitance

= 25

C, f = 1.0 MHz)

Symbol

Parameter

Min.

Max.

Unit

Conditions

Input Capacitance

= 0V

I/O

Input/Output Capacitance

I/O

= 0V

These parameters are sampled and not 100% tested.

A62L256 Series

PRELIMINARY (November, 2001, Version 1.4)

AMIC Technology, Inc.

AC Characteristics

= 0

C to +70

C or -40º C to +85º C)

Symbol

Parameter

A62L256-55LL/LLU

(VCC = 3.0V to 3.6V)

A62L256-70LL/LLU

(VCC = 2.7V to 3.6V)

Unit

Min.

Max.

Min.

Max.

Read Cycle

Read Cycle Time

Address Access Time

ACE

Chip Enable Access Time

Output Enable to Output Valid

CLZ

Chip Enable to Output in Low Z

OLZ

Output Enable to Output in Low Z

CHZ

Chip Disable to Output in High Z

OHZ

Output Disable to Output in High Z

Output Hold from Address Change

Write Cycle

Write Cycle Time

Chip Enable to End of Write

Address Set up Time

Address Valid to End of Write

Write Pulse Width

Write Recovery Time

WHZ

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Active from End of Write

Notes: t

CHZ

, t

OHZ

and t

WHZ

are defined as the time at which the outputs achieve the open circuit condition and are not

referred to output voltage levels.