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A29L160 Series

2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only,

Preliminary

Boot Sector Flash Memory

PRELIMINARY (July, 2002, Version 0.0)

AMIC Technology, Inc.

Features

Single power supply operation

- Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

- Regulated voltage range: 3.0 to 3.6 volt read and write

operations for compatibility with high performance 3.3

volt microprocessors

Access times:

- 70/90/120 (max.)

Current:

- 9 mA typical active read current

- 20 mA typical program/erase current

200 nA typical CMOS standby

200 nA Automatic Sleep Mode current

Flexible sector architecture

16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX31 sectors

8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX31 sectors

Any combination of sectors can be erased

Supports full chip erase

Sector protection:

A hardware method of protecting sectors to prevent

any inadvertent program or erase operations within

that sector. Temporary Sector Unprotect feature

allows code changes in previously locked sectors

Unlock Bypass Program Command

- Reduces overall programming time when issuing

multiple program command sequence

Top or bottom boot block configurations available

Embedded Algorithms

- Embedded Erase algorithm will automatically erase

the entire chip or any combination of designated

sectors and verify the erased sectors

- Embedded Program algorithm automatically writes and

verifies data at specified addresses

Typical 100,000 program/erase cycles per sector

20-year data retention at 125

Reliable operation for the life of the system

CFI (Common Flash Interface) compliant

- Provides device-specific information to the system,

allowing host software to easily reconfigure for

different Flash devices

Compatible with JEDEC-standards

- Pinout and software compatible with single-power-

supply Flash memory standard

Superior inadvertent write protection

Data

Polling and toggle bits

Provides a software method of detecting completion

of program or erase operations

Ready /

BUSY

pin (RY /

)

- Provides a hardware method of detecting completion

of program or erase operations (not available on 44-

pin SOP)

Erase Suspend/Erase Resume

Suspends a sector erase operation to read data from,

or program data to, a non-erasing sector, then

resumes the erase operation

Hardware reset pin (

RESET

)

Hardware method to reset the device to reading array

data

Package options

44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA

A29L160 Series

PRELIMINARY (July, 2002, Version 0.0)

AMIC Technology, Inc.

General Description

The A29L160 is a 16Mbit, 3.0 volt-only Flash memory

organized as 2,097,152 bytes of 8 bits or 1,048,576 words of

16 bits each. The 8 bits of data appear on I/O

- I/O

; the 16

bits of data appear on I/O

~I/O

. The A29L160 is offered in

48-ball FBGA,

44-pin SOP and 48-Pin TSOP packages. This

device is designed to be programmed in-system with the

standard system 3.0 volt VCC supply. Additional 12.0 volt

VPP is not required for in-system write or erase operations.

However, the A29L160 can also be programmed in standard

EPROM programmers.

The A29L160 has the first toggle bit, I/O

, which indicates

whether an Embedded Program or Erase is in progress, or it

is in the Erase Suspend. Besides the I/O

toggle bit, the

A29L160 has a second toggle bit, I/O

, to indicate whether

the addressed sector is being selected for erase. The

A29L160 also offers the ability to program in the Erase

Suspend mode. The standard A29L160 offers access times

of 70, 90 and 120ns, allowing high-speed microprocessors to

operate without wait states. To eliminate bus contention the

device has separate chip enable (

), write enable (

)

and output enable (

) controls.

The device requires only a single 3.0 volt power supply for

both read and write functions. Internally generated and

regulated voltages are provided for the program and erase

operations.

The A29L160 is entirely software command set compatible

with the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timings. Register contents

serve as input to an internal state-machine that controls the

erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and

erase operations. Reading data out of the device is similar to

reading from other Flash or EPROM devices.

Device programming occurs by writing the proper program

command sequence. This initiates the Embedded Program

algorithm - an internal algorithm that automatically times the

program pulse widths and verifies proper program margin.

Device erasure occurs by executing the proper erase

command sequence. This initiates the Embedded Erase

algorithm - an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper erase margin. The Unlock Bypass mode

facilitates faster programming times by requiring only two

write cycles to program data instead of four.

The host system can detect whether a program or erase

operation is complete by observing the RY /

pin, or

reading the I/O

(

Data

Polling) and I/O

(toggle) status bits.

After a program or erase cycle has been completed, the

device is ready to read array data or accept another

command.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data

contents of other sectors. The A29L160 is fully erased when

shipped from the factory.

The hardware sector protection feature disables operations

for both program and erase in any combination of the

sectors of memory. This can be achieved via programming

equipment.

The Erase Suspend/Erase Resume feature enables the user

to put erase on hold for any period of time to read data from,

or program data to, any other sector that is not selected for

erasure. True background erase can thus be achieved.

The hardware RESET pin terminates any operation in

progress and resets the internal state machine to reading

array data. The RESET pin may be tied to the system reset

circuitry. A system reset would thus also reset the device,

enabling the system microprocessor to read the boot-up

firmware from the Flash memory.

The device offers two power-saving features. When

addresses have been stable for a specified amount of time,

the device enters the automatic sleep mode. The system can

also place the device into the standby mode. Power

consumption is greatly reduced in both these modes.

A29L160 Series

PRELIMINARY (July, 2002, Version 0.0)

AMIC Technology, Inc.

Pin Configurations

SOP

TSOP (I)

A18

A17

VSS

I/O

(A-1)

VSS

BYTE

A16

A15

A14

A12

A11

A10

A19

A13

A29L160

RESET

I/O

VCC

A29L160V

A14

A13

A12

A11

A10

RESET

RY/BY

A18

I/O

VCC

I/O

(A-1)

VSS

BYTE

A16

A15

A19

I/O

VSS

A17

TFBGA

Top View, Balls Facing Down

A13

A12

A14

A15

A16

BYTE

I/O

(A-1)

VSS

A10

A11

I/O

RESET

A19

I/O

VCC

I/O

RY/BY

A18

I/O

A17

I/O

VSS

A29L160 Series

PRELIMINARY (July, 2002, Version 0.0)

AMIC Technology, Inc.

Absolute Maximum Ratings*

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . . . . . . .0

C to + 70

Ambient Temperature

with Power Applied . . . . . . . . . . . . . . . . . . . 0

C to + 70

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.0V

A9,

& RESET (Note 2) . . . . . . . . . . . . -0.5 to +12.5V

All other pins (Note 1) . . . . . . . . . . . . -0.5V to VCC + 0.5V

Output Short Circuit Current (Note 3) . . . . . . . . . 200mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5V. During

voltage transitions, input or I/O pins may undershoot

VSS to -2.0V for periods of up to 20ns. Maximum DC

voltage on input and I/O pins is VCC +0.5V. During

voltage transitions, input or I/O pins may

overshoot to

VCC +2.0V for periods up to 20ns.

2. Minimum DC input voltage on A9,

and RESET is -

0.5V. During voltage transitions, A9,

and RESET

may overshoot VSS to -2.0V for periods of up to 20ns.

Maximum DC input voltage on A9 is +12.5V which may

overshoot to 14.0V for periods up to 20ns.

3. No more than one output is shorted at a time. Duration

of the short circuit should not be greater than one

second.

*Comments

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to this device.

These are stress ratings only. Functional operation of

this device at these or any other conditions above

those indicated in the operational sections of these

specification is not implied or intended. Exposure to

the absolute maximum rating conditions for extended

periods may affect device reliability.

Operating Ranges

Commercial (C) Devices

Ambient Temperature (T

) . . . . . . . . . . . . . . 0

C to +70

VCC Supply Voltages

VCC for all devices . . . . . . . . . . . . . . . . . . +2.7V to +3.6V

Operating ranges define those limits between which the

functionally of the device is guaranteed.

Device Bus Operations

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register itself

does not occupy any addressable memory location. The

along with the address and data information needed to

execute the command. The contents of the register serve

as inputs to the internal state machine. The state machine

outputs dictate the function of the device. The appropriate

device bus operations table lists the inputs and control

levels required, and the resulting output. The following

subsections describe each of these operations in further

detail.

Table 1. A29L160 Device Bus Operations

I/O

- I/O

Operation

RESET

A0 – A19

(Note 1)

I/O

- I/O

BYTE

Read

OUT

I/O

~I/O

=High-Z

I/O

-1

Write

High-Z

CMOS Standby

VCC

0.3 V

X VCC

0.3 V

High-Z

Output Disable

High-Z

Hardware Reset

High-Z

Sector Protect

(See Note 2)

Sector Address,

A6=L, A1=H, A0=L

Sector Unprotect

(See Note 2)

Sector Address,

A6=H, A1=H, A0=L

Temporary Sector

Unprotect

Legend:

L = Logic Low = V

, H = Logic High = V

, V

= 12.0

0.5V, X = Don't Care, D

= Data In, D

OUT

= Data Out, A

= Address In

Notes:

1. Addresses are A19:A0 in word mode (

BYTE=V

), A19: A

-1

in byte mode (

BYTE=V

2. See the “Sector Protection/Unprotection” section and Temporary Sector Unprotect for more information.

A29L160 Series

PRELIMINARY (July, 2002, Version 0.0)

AMIC Technology, Inc.

Word/Byte Configuration

The

BYTE

pin determines whether the I/O pins I/O

-I/O

operate in the byte or word configuration. If the

BYTE

is set at logic ”1”, the device is in word configuration, I/O

I/O

are active and controlled by

and

If the

BYTE

pin is set at logic “0”, the device is in byte

configuration, and only I/O

-I/O

are active and controlled

and

. I/O

-I/O

are tri-stated, and I/O

pin is

used as an input for the LSB(A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive

the

and

pins to V

is the power control and

selects the device.

is the output control and gates

array data to the output pins.

should remain at V

all

the time during read operation. The

BYTE

pin determines

whether the device outputs array data in words and bytes.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory content

occurs during the power transition. No command is

necessary in this mode to obtain array data. Standard

microprocessor read cycles that assert valid addresses on

the device address inputs produce valid data on the device

data outputs. The device remains enabled for read access

until the command register contents are altered.

See "Reading Array Data" for more information. Refer to the

AC Read Operations table for timing specifications and to

the Read Operations Timings diagram for the timing

waveforms, l

CC1

in the DC Characteristics table represents

the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which

includes programming data to the device and erasing

sectors of memory), the system must drive

and

, and

to V

. For program operations, the

BYTE

determines whether the device accepts program data in

bytes or words, Refer to “Word/Byte Configuration” for more

information. The device features an Unlock Bypass mode to

facilitate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are required to

program a word or byte, instead of four. The “

Word / Byte Program Command Sequence” section has

details on programming data to the device using both

standard and Unlock Bypass command sequence. An

erase operation can erase one sector, multiple sectors, or

the entire device. The Sector Address Tables indicate the

address range that each sector occupies. A "sector

address" consists of the address inputs required to uniquely

select a sector. See the "Command Definitions" section for

details on erasing a sector or the entire chip, or

suspending/resuming the erase operation.

After the system writes the autoselect command sequence,

the device enters the autoselect mode. The system can

then read autoselect codes from the internal register (which

is separate from the memory array) on I/O

- I/O

. Standard

read cycle timings apply in this mode. Refer to the

"Autoselect Mode" and "Autoselect Command Sequence"

sections for more information.

CC2

in the DC Characteristics table represents the active

current specification for the write mode. The "AC

Characteristics" section contains timing specification tables

and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status bits

on I/O

- I/O

. Standard read cycle timings and I

read

specifications apply. Refer to "Write Operation Status" for

more information, and to each AC Characteristics section

for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it

can place the device in the standby mode. In this mode,

current consumption is greatly reduced, and the outputs are

placed in the high impedance state, independent of the

input.

The device enters the CMOS standby mode when the

& RESET pins are both held at VCC

0.3V. (Note that this

is a more restricted voltage range than V

.) If

and

RESET are held at V

, but not within VCC

0.3V, the

device will be in the standby mode, but the standby current

will be greater. The device requires the standard access

time (t

) before it is ready to read data.

If the device is deselected during erasure or programming,

the device draws active current until the operation is

completed.

CC3

and

CC4

in the DC Characteristics tables represent the

standby current specification.

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