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A29040A Series

512K X 8 Bit CMOS 5.0 Volt-only,

Preliminary

Uniform Sector Flash Memory

PRELIMINARY (August, 2001, Version 0.1)

AMIC Technology, Inc.

Features

5.0V

10% for read and write operations

Access times:

- 55/70/90 (max.)

Current:

- 20 mA typical active read current

- 30 mA typical program/erase current

- 1

A typical CMOS standby

Flexible sector architecture

8 uniform sectors of 64 Kbyte each

Any combination of sectors can be erased

Supports full chip erase

Sector protection:

A hardware method of protecting sectors to prevent

any inadvertent program or erase operations within

that sector

Embedded Erase Algorithms

- Embedded Erase algorithm will automatically erase

the entire chip or any combination of designated

sectors and verify the erased sectors

- Embedded Program algorithm automatically writes

and verifies bytes at specified addresses

Typical 100,000 program/erase cycles per sector

20-year data retention at 125

- Reliable operation for the life of the system

Compatible with JEDEC-standards

- Pinout and software compatible with single-power-

supply Flash memory standard

Superior inadvertent write protection

Data

Polling and toggle bits

Provides a software method of detecting completion

of program or erase operations

Erase Suspend/Erase Resume

Suspends a sector erase operation to read data from,

or program data to, a non-erasing sector, then

resumes the erase operation

Package options

32-pin P-DIP, PLCC, or TSOP (Forward type)

General Description

The A29040A is a 5.0 volt-only Flash memory organized as

524,288 bytes of 8 bits each. The 512 Kbytes of data are

further divided into eight sectors of 64 Kbytes each for flexible

sector erase capability. The 8 bits of data appear on I/O

- I/O

while the addresses are input on A0 to A18. The A29040A is

offered in 32-pin PLCC, TSOP, and PDIP packages. This

device is designed to be programmed in-system with the

standard system 5.0 volt VCC supply. Additional 12.0 volt VPP

is not required for in-system write or erase operations.

However, the A29040A can also be programmed in standard

EPROM programmers.

The A29040A has a second toggle bit, I/O

, to indicate

whether the addressed sector is being selected for erase, and

also offers the ability to program in the Erase Suspend mode.

The standard A29040A offers access times of 55, 70 and 90

ns, allowing high-speed microprocessors to operate without

wait states. To eliminate bus contention the device has

separate chip enable (

), write enable (

) and output

enable (

) controls.

The device requires only a single 5.0 volt power supply for

both read and write functions. Internally generated and

regulated voltages are provided for the program and erase

operations.

The A29040A is entirely software command set compatible

with the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timings. Register contents

serve as input to an internal state-machine that controls the

erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and

erase operations. Reading data out of the device is similar to

reading from other Flash or EPROM devices.

Device programming occurs by writing the proper program

command sequence. This initiates the Embedded Program

algorithm - an internal algorithm that automatically times the

program pulse widths and verifies proper program margin.

Device erasure occurs by executing the proper erase

command sequence. This initiates the Embedded Erase

algorithm - an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper erase margin.

A29040A Series

PRELIMINARY (August, 2001, Version 0.1)

AMIC Technology, Inc.

The host system can detect whether a program or erase

operation is complete by reading the I/O

(

Data

Polling) and

I/O

(toggle) status bits. After a program or erase cycle has

been completed, the device is ready to read array data or

accept another command.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data contents

of other sectors. The A29040A is fully erased when shipped

from the factory.

Pin Configurations

The hardware sector protection feature disables operations

for both program and erase in any combination of the sectors

of memory. This can be achieved via programming

equipment.

The Erase Suspend feature enables the user to put erase on

hold for any period of time to read data from, or program data

to, any other sector that is not selected for erasure. True

background erase can thus be achieved.

Power consumption is greatly reduced when the device is

placed in the standby mode.

DIP

PLCC

A18

A16

A15

A12

I/O

VSS

I/O

A10

A13

A17

A14

VCC

A11

A29040A

I/O

A10

A29040AL

A11

A13

A14

I/O

VSS

I/O

A12

A15

A16

A18

VCC

A17

TSOP (Forward type)

A29040AV

A13

A14

A17

VCC

A18

A16

A15

A12

I/O

VSS

I/O

A10

A11

A29040A Series

PRELIMINARY (August, 2001, Version 0.1)

AMIC Technology, Inc.

Absolute Maximum Ratings*

Ambient Operating Temperature . . . . . -55

C to + 125

Storage Temperature . . . . . . . . . . . . . . -65

C to + 125

VCC to Ground . . . . . . . . . . . . . . . . . . . . . . -2.0V to 7.0V

Output Voltage (Note 1) . . . . . . . . . . . . . . . -2.0V to 7.0V

A9 &

(Note 2) . . . . . . . . . . . . . . . . . . . -2.0V to 12.5V

All other pins (Note 1) . . . . . . . . . . . . . . . . . -2.0V to 7.0V

Output Short Circuit Current (Note 3) . . . . . . . . . . 200mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5V.

During voltage transitions, inputs may undershoot VSS

to -2.0V for periods of up to 20ns. Maximum DC voltage

on output and I/O pins is VCC +0.5V. During voltage

transitions, outputs may overshoot to VCC +2.0V for

periods up to 20ns.

2. Minimum DC input voltage on A9 pins is -0.5V. During

voltage transitions, A9 and

may overshoot VSS to

-2.0V for periods of up to 20ns. Maximum DC input

voltage on A9 and

is +12.5V which may overshoot

to 13.5V for periods up to 20ns.

3. No more than one output is shorted at a time. Duration

of the short circuit should not be greater than one

second.

*Comments

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to this device.

These are stress ratings only. Functional operation of

this device at these or any other conditions above

those indicated in the operational sections of these

specification is not implied or intended. Exposure to

the absolute maximum rating conditions for extended

periods may affect device reliability.

Operating Ranges

Commercial (C) Devices

Ambient Temperature (T

) . . . . . . . . . . . . . 0

C to +70

VCC Supply Voltages

VCC for

10% devices . . . . . . . . . . . . . +4.5V to +5.5V

Operating ranges define those limits between which the

functionally of the device is guaranteed.

Device Bus Operations

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register itself

does not occupy any addressable memory location. The

along with the address and data information needed to

execute the command. The contents of the register serve

as inputs to the internal state machine. The state machine

outputs dictate the function of the device. The appropriate

device bus operations table lists the inputs and control

levels required, and the resulting output. The following

subsections describe each of these operations in further

detail.

Table 1. A29040A Device Bus Operations

Operation

A0 – A18

I/O

- I/O

Read

OUT

Write

CMOS Standby

VCC

0.5 V

High-Z

TTL Standby

High-Z

Output Disable

High-Z

Legend:

L = Logic Low = V

, H = Logic High = V

, V

= 12.0

0.5V, X = Don't Care, D

= Data In, D

OUT

= Data Out, A

= Address In

Note: See the "Sector Protection/Unprotection" section, for more information.

A29040A Series

PRELIMINARY (August, 2001, Version 0.1)

AMIC Technology, Inc.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive

the

and

pins to V

is the power control and

selects the device.

is the output control and gates

array data to the output pins.

should remain at V

all

the time during read operation. The internal state machine

is set for reading array data upon device power-up, or after

a hardware reset. This ensures that no spurious alteration

of the memory content occurs during the power transition.

No command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid data

on the device data outputs. The device remains enabled for

read access until the command register contents are

altered.

See "Reading Array Data" for more information. Refer to the

AC Read Operations table for timing specifications and to

the Read Operations Timings diagram for the timing

waveforms, l

CC1

in the DC Characteristics table represents

the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which

includes programming data to the device and erasing

sectors of memory), the system must drive

and

, and

to V

. An erase operation can erase one

sector, multiple sectors, or the entire device. The Sector

Address Tables indicate the address range that each sector

occupies. A "sector address" consists of the address inputs

required to uniquely select a sector. See the "Command

Definitions" section for details on erasing a sector or the

entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence,

the device enters the autoselect mode. The system can

then read autoselect codes from the internal register (which

is separate from the memory array) on I/O

- I/O

. Standard

read cycle timings apply in this mode. Refer to the

"Autoselect Mode" and "Autoselect Command Sequence"

sections for more information.

CC2

in the Characteristics table represents the active

current specification for the write mode. The "AC

Characteristics" section contains timing specification tables

and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status bits

on I/O

- I/O

. Standard read cycle timings and I

read

specifications apply. Refer to "Write Operation Status" for

more information, and to each AC Characteristics section

for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it

can place the device in the standby mode. In this mode,

current consumption is greatly reduced, and the outputs are

placed in the high impedance state, independent of the

input.

The device enters the CMOS standby mode when the

pin is held at V

0.5V. (Note that this is a more restricted

voltage range than V

.) The device enters the TTL standby

mode when

is held at V

. The device requires the

standard access time (t

) before it is ready to read data.

If the device is deselected during erasure or programming,

the device draws active current until the operation is

completed.

CC3

in the DC Characteristics tables represents the standby

current specification.

Output Disable Mode

When the

input is at V

, output from the device is

disabled. The output pins are placed in the high impedance

state.

Table 2. Sector Addresses Table

Sector

A18

A17

A16

Address Range

SA0

00000h - 0FFFFh

SA1

10000h - 1FFFFh

SA2

20000h - 2FFFFh

SA3

30000h - 3FFFFh

SA4

40000h - 4FFFFh

SA5

50000h - 5FFFFh

SA6

60000h - 6FFFFh

SA7

70000h - 7FFFFh

Note: All sectors are 64 Kbytes in size.

A29040A Series

PRELIMINARY (August, 2001, Version 0.1)

AMIC Technology, Inc.

Autoselect Mode

The autoselect mode provides manufacturer and device

identification, and sector protection verification, through

identifier codes output on I/O

- I/O

. This mode is primarily

intended for programming equipment to automatically

match a device to be programmed with its corresponding

programming algorithm. However, the autoselect codes

can also be accessed in-system through the command

When using programming equipment, the autoselect mode

requires V

(11.5V to 12.5 V) on address pinA9. Address

pins A6, A1, and AO must be as shown in Autoselect

Codes (High Voltage Method) table. In addition, when

verifying sector protection, the sector address must appear

on the appropriate highest order address bits. Refer to the

corresponding Sector Address Tables. The Command

Definitions table shows the remaining address bits that are

don't care. When all necessary bits have been set as

required, the programming equipment may then read the

corresponding identifier code on I/O

- I/O

.To access the

autoselect codes in-system, the host system can issue the

autoselect command via the command register, as shown

in the Command Definitions table. This method does not

require V

. See "Command Definitions" for details on

using the autoselect mode.

Table 3. A29040A Autoselect Codes (High Voltage Method)

Description

A18 - A16 A15 - A10 A9 A8 - A7 A6 A5 - A2 A1

Identifier Code on

I/O

- I/O

Manufacturer ID: AMIC

37h

Device ID: A29040A

86h

0lh (protected)

Sector Protection

Verification

Sector

Address

00h (unprotected)

Continuation ID

7Fh

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The hardware

sector unprotection feature re-enables both program and

erase operations in previously protected sectors.

Sector protection/unprotection must be implemented using

programming equipment. The procedure requires a high

voltage (V

) on address pin A9 and the control pins.

The device is shipped with all sectors unprotected.

It is possible to determine whether a sector is protected or

unprotected. See "Autoselect Mode" for details.

Hardware Data Protection

The requirement of command unlocking sequence for

programming or erasing provides data protection against

inadvertent writes (refer to the Command Definitions table).

In addition, the following hardware data protection measures

prevent accidental erasure or programming, which might

otherwise be caused by spurious system level signals during

power-up transitions, or from system noise. The device

is powered up to read array data to avoid accidentally writing

data to the array.

Write Pulse "Glitch" Protection

Noise pulses of less than 5ns (typical) on

do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of

= V

. To initiate a write cycle,

and

must be a logical zero while

is a logical one.

Power-Up Write Inhibit

= V

and

= V

during power up, the

device does not accept commands on the rising edge of

. The internal state machine is automatically reset to

reading array data on the initial power-up.

A29040A Series

PRELIMINARY (August, 2001, Version 0.1)

AMIC Technology, Inc.

Command Definitions

Writing specific address and data commands or sequences

into the command register initiates device operations. The

Command Definitions table defines the valid register

command sequences. Writing incorrect address and data

values or writing them in the improper sequence resets the

device to reading array data.

All addresses are latched on the falling edge of

whichever happens later. All data is latched on the rising

edge of

, whichever happens first. Refer to the

appropriate timing diagrams in the "AC Characteristics"

section.

Reading Array Data

The device is automatically set to reading array data after

device power-up. No commands are required to retrieve

data. The device is also ready to read array data after

completing an Embedded Program or Embedded Erase

algorithm. After the device accepts an Erase Suspend

command, the device enters the Erase Suspend mode. The

system can read array data using the standard read timings,

except that if it reads at an address within erase-suspended

sectors, the device outputs status data. After completing a

programming operation in the Erase Suspend mode, the

system may once again read array data with the same

exception. See "Erase Suspend/Erase Resume Commands"

for more information on this mode.

The system must issue the reset command to re-enable the

device for reading array data if I/O

goes high, or while in the

autoselect mode. See the "Reset Command" section, next.

See also "Requirements for Reading Array Data" in the

"Device Bus Operations" section for more information. The

Read Operations table provides the read parameters, and

Read Operation Timings diagram shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to

reading array data. Address bits are don't care for this

command. The reset command may be written between the

sequence cycles in an erase command sequence before

erasing begins. This resets the device to reading array data.

Once erasure begins, however, the device ignores reset

commands until the operation is complete.

The reset command may be written between the sequence

cycles in a program command sequence before

programming begins. This resets the device to reading array

data (also applies to programming in Erase Suspend mode).

Once programming begins, however, the device ignores

reset commands until the operation is complete.

The reset command may be written between the sequence

cycles in an autoselect command sequence. Once in the

autoselect mode, the reset command must be written to

return to reading array data (also applies to autoselect

during Erase Suspend).

If I/O

goes high during a program or erase operation, writing

the reset command returns the device to reading array data

(also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system

to access the manufacturer and devices codes, and

determine whether or not a sector is protected. The

Command Definitions table shows the address and data

requirements. This method is an alternative to that shown in

the Autoselect Codes (High Voltage Method) table, which is

intended for PROM programmers and requires V

address bit A9.

The autoselect command sequence is initiated by writing two

unlock cycles, followed by the autoselect command. The

device then enters the autoselect mode, and the system

may read at any address any number of times, without

initiating another command sequence.

A read cycle at address XX00h retrieves the manufacturer

code and another read cycle at XX11h retrieves the

continuation code. A read cycle at address XX01h returns

the device code. A read cycle containing a sector address

(SA) and the address 02h in returns 01h if that sector is

protected, or 00h if it is unprotected. Refer to the Sector

Address tables f