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A29001/290011 Series

128K X 8 Bit CMOS 5.0 Volt-only,

Preliminary

Boot Sector Flash Memory

PRELIMINARY (August, 2001, Version 0.3)

AMIC Technology, Inc.

Features

5.0V

10% for read and write operations

Access times:

- 55/70/90 (max.)

Current:

- 20 mA typical active read current

- 30 mA typical program/erase current

- 1

A typical CMOS standby

Flexible sector architecture

8 Kbyte/ 4 KbyteX2/ 16 Kbyte/ 32 KbyteX3 sectors

Any combination of sectors can be erased

Supports full chip erase

Sector protection:

A hardware method of protecting sectors to prevent

any inadvertent program or erase operations within

that sector

Top or bottom boot block configurations available

Embedded Erase Algorithms

- Embedded Erase algorithm will automatically erase the

entire chip or any combination of designated sectors

and verify the erased sectors

- Embedded Program algorithm automatically writes and

verifies bytes at specified addresses

Typical 100,000 program/erase cycles per sector

20-year data retention at 125

- Reliable operation for the life of the system

Compatible with JEDEC-standards

- Pinout and software compatible with single-power-

supply Flash memory standard

Superior inadvertent write protection

Data

Polling and toggle bits

Provides a software method of detecting completion of

program or erase operations

Erase Suspend/Erase Resume

Suspends a sector erase operation to read data from,

or program data to, a non-erasing sector, then

resumes the erase operation

Hardware reset pin (

RESET

)

Hardware method to reset the device to reading array

data (not available on A290011)

Package options

32-pin P-DIP, PLCC, or TSOP (Forward type)

General Description

The A29001 is a 5.0 volt-only Flash memory organized as

131,072 bytes of 8 bits each. The A29001 offers the

RESET

function, but it is not available on A290011. The 128 Kbytes of

data are further divided into seven sectors for flexible sector

erase capability. The 8 bits of data appear on I/O

- I/O

while

the addresses are input on A0 to A16. The A29001 is offered in

32-pin PLCC, TSOP, and PDIP packages. This device is

designed to be programmed in-system with the standard

system 5.0 volt VCC supply. Additional 12.0 volt VPP is not

required for in-system write or erase operations. However, the

A29001 can also be programmed in standard EPROM

programmers.

The A29001 has the first toggle bit, I/O

, which indicates

whether an Embedded Program or Erase is in progress, or it is

in the Erase Suspend. Besides the I/O

toggle bit, the A29001

has a second toggle bit, I/O

, to indicate whether the

addressed sector is being selected for erase. The A29001 also

offers the ability to program in the Erase Suspend mode. The

standard A29001 offers access times of 55, 70 and 90 ns

allowing high-speed microprocessors to operate without wait

states. To eliminate bus contention the device has separate

chip enable (

), write enable (

) and output enable (

)

controls.

The device requires only a single 5.0 volt power supply for both

read and write functions. Internally generated and regulated

voltages are provided for the program and erase operations.

The A29001 is entirely software command set compatible with

the JEDEC single-power-supply Flash standard. Commands

are written to the command register using standard

microprocessor write timings. Register contents serve as input

to an internal state-machine that controls the erase and

programming circuitry. Write cycles also internally latch

addresses and data needed for the programming and erase

operations. Reading data out of the device is similar to reading

from other Flash or EPROM devices.

Device programming occurs by writing the proper program

command sequence. This initiates the Embedded Program

algorithm - an internal algorithm that automatically times the

program pulse widths and verifies proper program margin.

Device erasure occurs by executing the proper erase

command sequence. This initiates the Embedded Erase

algorithm - an internal algorithm that automatically

preprograms the array (if it is not already programmed) before

executing the erase operation. During erase, the device

automatically times the erase pulse widths and verifies proper

erase margin.

A29001/A290011 Series

PRELIMINARY (August, 2001, Version 0.3)

AMIC Technology, Inc.

The host system can detect whether a program or erase

operation is complete by reading the I/O

(

Data

Polling) and

I/O

(toggle) status bits. After a program or erase cycle has

been completed, the device is ready to read array data or

accept another command.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data contents

of other sectors. The A29001 is fully erased when shipped

from the factory.

The hardware sector protection feature disables operations for

both program and erase in any combination of the sectors

Pin Configurations

of memory. This can be achieved via programming

equipment.

The Erase Suspend feature enables the user to put erase on

hold for any period of time to read data from, or program data

to, any other sector that is not selected for erasure. True

background erase can thus be achieved.

Power consumption is greatly reduced when the device is

placed in the standby mode.

The hardware RESET pin terminates any operation in

progress and resets the internal state machine to reading

array data (This feature is not available on the A290021).

DIP

PLCC

RESET

A16

A15

A12

I/O

VSS

I/O

A10

A13

A14

VCC

A11

A29001/A290011

I/O

A10

A29001L/

A290011L

A11

A13

A14

I/O

VSS

I/O

A12

A15

A16

RESET

VCC

NC on A290011

TSOP (Forward type)

A29001V/A290011V

A13

A14

VCC

A16

A15

A12

I/O

VSS

I/O

A10

A11

RESET

NC on A290011

A29001/A290011 Series

PRELIMINARY (August, 2001, Version 0.3)

AMIC Technology, Inc.

Absolute Maximum Ratings*

Ambient Operating Temperature . . . . . -55

C to + 125

Storage Temperature . . . . . . . . . . . . . . -65

C to + 125

Ground to VCC . . . . . . . . . . . . . . . . . . . . . . -2.0V to 7.0V

Output Voltage (Note 1) . . . . . . . . . . . . . . . -2.0V to 7.0V

A9,

& RESET (Note 2) . . . . . . . . . . . -2.0V to 12.5V

All other pins (Note 1) . . . . . . . . . . . . . . . . . -2.0V to 7.0V

Output Short Circuit Current (Note 3) . . . . . . . . . . 200mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5V.

During voltage transitions, inputs may undershoot VSS

to -2.0V for periods of up to 20ns. Maximum DC voltage

on output and I/O pins is VCC +0.5V. During voltage

transitions, outputs may overshoot to VCC +2.0V for

periods up to 20ns.

2. Minimum DC input voltage on A9 pins is -0.5V. During

voltage transitions, A9,

and RESET may overshoot

VSS to -2.0V for periods of up to 20ns. Maximum DC

input voltage on A9 and

is +12.5V which may

overshoot to 13.5V for periods up to 20ns. (RESET is

N/A on A290021)

3. No more than one output is shorted at a time. Duration

of the short circuit should not be greater than one

second.

*Comments

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to this device.

These are stress ratings only. Functional operation of

this device at these or any other conditions above

those indicated in the operational sections of these

specification is not implied or intended. Exposure to

the absolute maximum rating conditions for extended

periods may affect device reliability.

Operating Ranges

Commercial (C) Devices

Ambient Temperature (T

) . . . . . . . . . . . . . . 0

C to +70

VCC Supply Voltages

VCC for

10% devices . . . . . . . . . . . . . . +4.5V to +5.5V

Operating ranges define those limits between which the

functionally of the device is guaranteed.

Device Bus Operations

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register itself

does not occupy any addressable memory location. The

along with the address and data information needed to

execute the command. The contents of the register serve

as inputs to the internal state machine. The state machine

outputs dictate the function of the device. The appropriate

device bus operations table lists the inputs and control

levels required, and the resulting output. The following

subsections describe each of these operations in further

detail.

Table 1. A29001/A290011 Device Bus Operations

Operation

RESET

(N/A A290011)

A0 – A16

I/O

- I/O

Read

OUT

Write

CMOS Standby

VCC

0.5 V

VCC

0.5 V

High-Z

TTL Standby

VCC

0.5 V

High-Z

Output Disable

High-Z

Reset

High-Z

Temporary Sector Unprotect (Note)

Legend:

L = Logic Low = V

, H = Logic High = V

, V

= 12.0

0.5V, X = Don't Care, D

= Data In, D

OUT

= Data Out, A

= Address In

Note: 1. See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information.

2. This function is not available on A290011.

A29001/A290011 Series

PRELIMINARY (August, 2001, Version 0.3)

AMIC Technology, Inc.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive

the

and

pins to V

is the power control and

selects the device.

is the output control and gates

array data to the output pins.

should remain at V

all

the time during read operation. The internal state machine

is set for reading array data upon device power-up, or after

a hardware reset. This ensures that no spurious alteration

of the memory content occurs during the power transition.

No command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid data

on the device data outputs. The device remains enabled for

read access until the command register contents are

altered.

See "Reading Array Data" for more information. Refer to the

AC Read Operations table for timing specifications and to

the Read Operations Timings diagram for the timing

waveforms, l

CC1

in the DC Characteristics table represents

the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which

includes programming data to the device and erasing

sectors of memory), the system must drive

and

, and

to V

. An erase operation can erase one

sector, multiple sectors, or the entire device. The Sector

Address Tables indicate the address range that each sector

occupies. A "sector address" consists of the address inputs

required to uniquely select a sector. See the "Command

Definitions" section for details on erasing a sector or the

entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence,

the device enters the autoselect mode. The system can

then read autoselect codes from the internal register (which

is separate from the memory array) on I/O

- I/O

. Standard

read cycle timings apply in this mode. Refer to the

"Autoselect Mode" and "Autoselect Command Sequence"

sections for more information.

CC2

in the Characteristics table represents the active

current specification for the write mode. The "AC

Characteristics" section contains timing specification tables

and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status bits

on I/O

- I/O

. Standard read cycle timings and I

read

specifications apply. Refer to "Write Operation Status" for

Standby Mode

When the system is not reading or writing to the device, it

can place the device in the standby mode. In this mode,

current consumption is greatly reduced, and the outputs are

placed in the high impedance state, independent of the

input.

The device enters the CMOS standby mode when the

& RESET pins (

only on A290011) are both held at V

0.5V. (Note that this is a more restricted voltage range

than V

.) The device enters the TTL standby mode when

is held at V

, while RESET (Not available on

A290011) is held at VCC

0.5V. The device requires the

standard access time (t

) before it is ready to read data.

If the device is deselected during erasure or programming,

the device draws active current until the operation is

completed.

CC3

in the DC Characteristics tables represents the standby

current specification.

Output Disable Mode

When the

input is at V

, output from the device is

disabled. The output pins are placed in the high impedance

state.

RESET

: Hardware Reset Pin (N/A on A290011)

The RESET pin provides a hardware method of resetting

the device to reading array data. When the system drives

the RESET pin low for at least a period of t

, the device

immediately terminates any operation in progress, tristates

all data output pins, and ignores all read/write attempts for

the duration of the RESET pulse. The device also resets

the internal state machine to reading array data. The

operation that was interrupted should be reinitiated once

the device is ready to accept another command sequence,

to ensure data integrity.

The RESET pin may be tied to the system reset circuitry. A

system reset would thus also reset the Flash memory,

enabling the system to read the boot-up firmware from the

Flash memory.

Refer to the AC Characteristics tables for RESET

parameters and diagram.

more information, and to each AC Characteristics section

for timing diagrams.

A29001/A290011 Series

PRELIMINARY (August, 2001, Version 0.3)

AMIC Technology, Inc.

Table 2. A29001/A290011 Top Boot Block Sector Address Table

Sector

A16

A15

A14

A13

A12

Sector Size

(Kbytes)

Address Range

SA0

00000h - 07FFFh

SA1

08000h - 0FFFFh

SA2

10000h - 17FFFh

SA3

18000h - 1BFFFh

SA4

1C000h - 1CFFFh

SA5

1D000h - 1DFFFh

SA6

1E000h - 1FFFFh

Table 3. A29001/A290011 Bottom Boot Block Sector Address Table

Sector

A16

A15

A14

A13

A12

Sector Size

(Kbytes)

Address Range

SA0

00000h - 01FFFh

SA1

02000h - 02FFFh

SA2

03000h - 03FFFh

SA3

04000h - 07FFFh

SA4

08000h - 0FFFFh

SA5

10000h - 17FFFh

SA6

18000h - 1FFFFh

Autoselect Mode

The autoselect mode provides manufacturer and device

identification, and sector protection verification, through

identifier codes output on I/O

- I/O

. This mode is primarily

intended for programming equipment to automatically

match a device to be programmed with its corresponding

programming algorithm. However, the autoselect codes

can also be accessed in-system through the command

When using programming equipment, the autoselect mode

requires V

(11.5V to 12.5 V) on address pinA9. Address

pins A6, A1, and AO must be as shown in Autoselect

Codes (High Voltage Method) table. In addition, when

verifying sector protection, the sector address must appear

on the appropriate highest order address bits. Refer to the

corresponding Sector Address Tables. The Command

Definitions table shows the remaining address bits that are

don't care. When all necessary bits have been set as

required, the programming equipment may then read the

corresponding identifier code on I/O

- I/O

.To access the

autoselect codes in-system, the host system can issue the

autoselect command via the command register, as shown

in the Command Definitions table. This method does not

require V

. See "Command Definitions" for details on

using the autoselect mode.

Table 4. A29001/A290011 Autoselect Codes (High Voltage Method)

Description

A16 - A12 A11 - A10 A9 A8 - A7 A6 A5 - A2 A1

Identifier Code on

I/O

- I/O

Manufacturer ID: AMIC

37h

Device ID: A29001/

A290011

Top Boot Block: A1h

Bottom Boot Block: 4Ch

0lh (protected)

Sector Protection

Verification

Sector

Address

00h (unprotected)

Continuation ID

7Fh

Note: CE

and

when Autoselect Mode