SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430 – MAY 1999
1
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
D
EPIC
™
(Enhanced-Performance Implanted
CMOS) Process
D
High On-Off Output-Voltage Ratio
D
Low Crosstalk Between Switches
D
Individual Switch Controls
D
Extremely Low Input Current
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), Ceramic Flat
(W) Packages, and Standard Plastic (N) and
Ceramic (J) DIPs
description
These triple 2-channel CMOS analog multiplexers/demultiplexers are designed for 2-V to 5.5-V V
CC
operation.
The ’LV4053A devices handle both analog and digital signals. Each channel permits signals with amplitudes
up to 5.5 V (peak) to be transmitted in either direction.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
The SN54LV4053A is characterized for operation over the full military temperature range of –55
°
C to 125
°
C.
The SN74LV4053A is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
INPUTS
ON CHANNELS
INH
C
B
A
ON CHANNELS
L
L
L
L
1Y0, 2Y0, 3Y0
L
L
L
H
1Y1, 2Y0, 3Y0
L
L
H
L
1Y0, 2Y1, 3Y0
L
L
H
H
1Y1, 2Y1, 3Y0
L
H
L
L
1Y0, 2Y0, 3Y1
L
H
L
H
1Y1, 2Y0, 3Y1
L
H
H
L
1Y0, 2Y1, 3Y1
L
H
H
H
1Y1, 2Y1, 3Y1
H
X
X
X
None
Copyright
©
1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2Y1
2Y0
3Y1
3-COM
3Y0
INH
GND
GND
V
CC
2-COM
1-COM
1Y1
1Y0
A
B
C
SN54LV4053A . . . J OR W PACKAGE
SN74LV4053A . . . D, DB, DGV, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430 – MAY 1999
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
logic symbol
†
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
MUXDMUX
G2
6
INH
2X0
11
A
2X1
1-COM
14
0, 1
1Y0
12
0
1Y1
13
1
10
B
2-COM
15
2Y0
2
2Y1
1
9
C
3-COM
4
3Y0
5
3Y1
3
logic diagram (positive logic)
1Y0
1Y1
2Y0
2Y1
3Y0
1-COM
INH
B
A
3-COM
3Y1
2-COM
C
11
10
9
6
15
14
12
13
2
1
5
3
4
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430 – MAY 1999
3
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
–0.5 V to 7.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch I/O voltage range, V
IO
(see Note 1 and Note 2)
–0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
–20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O diode current, I
IOK
(V
IO
< 0 or V
IO
> V
CC
)
±
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch through current, I
T
(V
IO
= 0 to V
CC
)
±
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
±
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
θ
JA
(see Note 3): D package
113
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package
131
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
180
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
78
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
111
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
149
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions (see Note 4)
SN74LV4053A
SN74LV4053A
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
2‡
5.5
2‡
5.5
V
VCC = 2 V
1.5
1.5
VIH
High level input voltage control inputs
VCC = 2.3 V to 2.7 V
VCC
×
0.7
VCC
×
0.7
V
VIH
High-level input voltage, control inputs
VCC = 3 V to 3.6 V
VCC
×
0.7
VCC
×
0.7
V
VCC = 4.5 V to 5.5 V
VCC
×
0.7
VCC
×
0.7
VCC = 2 V
0.5
0.5
VIL
Low level input voltage control inputs
VCC = 2.3 V to 2.7 V
VCC
×
0.3
VCC
×
0.3
V
VIL
Low-level input voltage, control inputs
VCC = 3 V to 3.6 V
VCC
×
0.3
VCC
×
0.3
V
VCC = 4.5 V to 5.5 V
VCC
×
0.3
VCC
×
0.3
VI
Control input voltage
0
5.5
0
5.5
V
VIO
Input/output voltage
0
VCC
0
VCC
V
VCC = 2.3 V to 2.7 V
0
200
0
200
∆
t/
∆
v
Input transition rise or fall rate
VCC = 3 V to 3.6 V
0
100
0
100
ns/V
VCC = 4.5 V to 5.5 V
0
20
0
20
TA
Operating free-air temperature
–55
125
–40
85
°
C
‡ With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals
be transmitted at these low supply voltages.
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430 – MAY 1999
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST
V
TA = 25
°
C
SN54LV4053A
SN74LV4053A
UNIT
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
O
t t
IT = 2 mA,
V
V
GND
2.3 V
41
180
225
225
Ron
On-state
switch resistance
VI = VCC or GND,
VINH = VIL
3 V
30
150
190
190
Ω
switch resistance
VINH = VIL
(see Figure 1)
4.5 V
23
75
100
100
IT = 2 mA,
2.3 V
139
500
600
600
Ron(P)
Peak on-state resistance
IT = 2 mA,
VI = VCC to GND,
3 V
63
180
225
225
Ω
( )
VINH = VIL
4.5 V
35
100
125
125
Difference in
IT = 2 mA,
2.3 V
2
30
40
40
∆
Ron
Difference in
on-state resistance
IT = 2 mA,
VI = VCC to GND,
3 V
1.6
20
30
30
Ω
between switches
VINH = VIL
4.5 V
1.3
15
20
20
II
Control input current
VI = VCC or GND
5.5 V
±
0.1
±
1
±
1
µ
A
Isoff
Off-state
switch leakage current
VI = VCC and
VO = GND, or
VI = GND and
VO = VCC,
VINH = VIH
(see Figure 2)
5.5 V
±
0.1
±
1
±
1
µ
A
Ison
On-state
switch leakage current
VI = VCC or GND,
VINH = VIH
(see Figure 3)
5.5 V
±
0.1
±
1
±
1
µ
A
ICC
Supply current
VI = VCC or GND
5.5 V
20
20
µ
A
CIC
Control input capacitance
2
pF
CIS
Common
terminal capacitance
8.2
pF
COS
Switch
terminal capacitance
5.6
pF
CT
Feed-through capacitance
0.5
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430 – MAY 1999
5
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 2.5 V
±
0.2 V (unless otherwise noted)
PARAMETER
FROM
TO
TEST
TA = 25
°
C
SN54LV4053A
SN74LV4053A
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH,
tPHL
Propagation
delay time
COM or
Yn
Yn or
COM
CL = 15 pF,
(see Figure 4)
2.5
10
16
16
ns
tPZH,
tPZL
Enable
delay time
INH
COM or
Yn
CL = 15 pF,
(see Figure 5)
7.6
18
23
23
ns
tPHZ,
tPLZ
Disable
delay time
INH
COM or
Yn
CL = 15 pF,
(see Figure 5)
7.7
18
23
23
ns
tPLH,
tPHL
Propagation
delay time
COM or
Yn
Yn or
COM
CL = 50 pF,
(see Figure 4)
4.4
12
18
18
ns
tPZH,
tPZL
Enable
delay time
INH
COM or
Yn
CL = 50 pF,
(see Figure 5)
8.8
28
35
35
ns
tPHZ,
tPLZ
Disable
delay time
INH
COM or
Yn
CL = 50 pF,
(see Figure 5)
11.7
28
35
35
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
±
0.3 V (unless otherwise noted)
PARAMETER
FROM
TO
TEST
TA = 25
°
C
SN54LV4053A
SN74LV4053A
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH,
tPHL
Propagation
delay time
COM or
Yn
Yn or
COM
CL = 15 pF,
(see Figure 4)
1.6
6
10
10
ns
tPZH,
tPZL
Enable
delay time
INH
COM or
Yn
CL = 15 pF,
(see Figure 5)
5.3
12
15
15
ns
tPHZ,
tPLZ
Disable
delay time
INH
COM or
Yn
CL = 15 pF,
(see Figure 5)
6.1
12
15
15
ns
tPLH,
tPHL
Propagation
delay time
COM or
Yn
Yn or
COM
CL = 50 pF,
(see Figure 4)
2.9
9
12
12
ns
tPZH,
tPZL
Enable
delay time
INH
COM or
Yn
CL = 50 pF,
(see Figure 5)
6.1
20
25
25
ns
tPHZ,
tPLZ
Disable
delay time
INH
COM or
Yn
CL = 50 pF,
(see Figure 5)
8.9
20
25
25
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430 – MAY 1999
6
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted)
PARAMETER
FROM
TO
TEST
TA = 25
°
C
SN54LV4053A
SN74LV4053A
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH,
tPHL
Propagation
delay time
COM or
Yn
Yn or
COM
CL = 15 pF,
(see Figure 4)
0.9
4
7
7
ns
tPZH,
tPZL
Enable delay
time
INH
COM or
Yn
CL = 15 pF,
(see Figure 5)
3.8
8
10
10
ns
tPHZ,
tPLZ
Disable
delay time
INH
COM or
Yn
CL = 15 pF,
(see Figure 5)
4.6
8
10
10
ns
tPLH,
tPHL
Propagation
delay time
COM or
Yn
Yn or
COM
CL = 50 pF,
(see Figure 4)
1.8
6
8
8
ns
tPZH,
tPZL
Enable delay
time
INH
COM or
Yn
CL = 50 pF,
(see Figure 5)
4.3
14
18
18
ns
tPHZ,
tPLZ
Disable
delay time
INH
COM or
Yn
CL = 50 pF,
(see Figure 5)
6.3
14
18
18
ns
analog switch characteristics
PARAMETER
FROM
TO
TEST CONDITIONS
VCC
TA = 25
°
C
UNIT
PARAMETER
(INPUT)
(OUTPUT)
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
F
CL = 50 pF,
R
600
Ω
2.3 V
30
Frequency response
(switch on)
COM or Yn
Yn or COM
RL = 600
Ω
,
fin = 1 MHz (sine wave)
3 V
35
MHz
(switch on)
fin = 1 MHz (sine wave)
(see Note 5 and Figure 6)
4.5 V
50
CL = 50 pF,
2.3 V
–45
Crosstalk
(between any switches)
COM or Yn
Yn or COM
RL = 600
Ω
,
fin = 1 MHz (sine wave)
3 V
–45
dB
(between any switches)
fin = 1 MHz (sine wave)
(see Note 6 and Figure 7)
4.5 V
–45
CL = 50 pF,
2.3 V
20
Crosstalk
(control input to signal output)
INH
COM or Yn
RL = 600
Ω
,
fin = 1 MHz (square wave)
3 V
35
mV
(control in ut to signal out ut)
fin = 1 MHz (square wave)
(see Figure 8)
4.5 V
65
CL = 50 pF,
2.3 V
–45
Feedthrough attenuation
(switch off)
COM or Yn
Yn or COM
RL = 600
Ω
,
fin = 1 MHz
3 V
–45
dB
(switch off)
fin = 1 MHz
(see Note 6 and Figure 9)
4.5 V
–45
CL = 50 pF,
RL = 10 k
Ω
VI = 2 Vp-p
2.3 V
0.1
Sine-wave distortion
COM or Yn
Yn or COM
RL = 10 k
Ω
,
fin = 1 kHz
( i
)
VI = 2.5 Vp-p
3 V
0.1
(sine wave)
(see Figure 10)
VI = 4 Vp-p
4.5 V
0.1
NOTES:
5. Adjust fin voltage to obtain 0-dBm output. Increase fin frequency until dB meter reads –3 dB.
6. Adjust fin voltage to obtain 0-dBm input.
operating characteristics, V
CC
= 3.3 V, T
A
= 25
°
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
f = 10 MHz
5.3
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430 – MAY 1999
7
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC
VI = VCC or GND
VINH = VIL
2 mA
VO
R
ON
+
V
I
– V
O
2
10
–3
W
VI – VO
VCC
GND
(ON)
V
Figure 1. On-State Resistance Test Circuit
VINH = VIH
VI
VO
Condition 1: VI = 0, VO = VCC
Condition 2: VI = VCC, VO = 0
A
VCC
VCC
GND
(OFF)
Figure 2. Off-State Switch Leakage-Current Test Circuit
VCC
VINH = VIL
VI