SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700D – JULY 1997 – REVISED APRIL 1999
1
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
™
Family
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
CC
)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
UBT
™
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
D
I
off
and Power-Up 3-State Support Hot
Insertion
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’LVTH16501 devices are 18-bit universal bus transceivers designed for low-voltage (3.3-V) V
CC
operation,
but with the capability to provide a TTL interface to a 5-V system environment.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the
outputs are active. When OEAB is low, the outputs are in the high-impedance state.
Copyright
©
1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and UBT are trademarks of Texas Instruments Incorporated.
SN54LVTH16501 . . . WD PACKAGE
SN74LVTH16501 . . . DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEAB
LEAB
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
OEBA
LEBA
GND
CLKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CLKBA
GND
SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700D – JULY 1997 – REVISED APRIL 1999
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
description (continued)
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V
CC
is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
CC
through a pullup resistor
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVTH16501 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C.
The SN74LVTH16501 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE†
INPUTS
OUTPUT
OEAB
LEAB
CLKAB
A
B
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
=
L
L
H
L
↑
H
H
H
L
H
X
B0‡
H
L
L
X
B0§
† A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA, LEBA, and CLKBA.
‡ Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was high before LEAB went low
§ Output level before the indicated steady-state input
conditions were established
SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700D – JULY 1997 – REVISED APRIL 1999
3
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
logic symbol
†
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
A2
5
EN1
1
OEAB
2C3
3D
3
A1
B1
54
A14
20
A15
21
A16
23
A17
24
A8
13
A9
14
A10
15
A11
16
A12
17
A3
6
A4
8
A5
9
A6
10
A7
12
B13
38
B14
37
B15
36
B16
34
B17
33
B18
31
6D
4
A18
26
B8
44
B9
43
B10
42
B11
41
B12
40
B3
51
B4
49
B5
48
B6
47
B7
45
B2
52
C6
28
LEBA
G5
30
CLKBA
EN4
27
C3
2
LEAB
G2
55
CLKAB
5C6
OEBA
1
1
1
A13
19
SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700D – JULY 1997 – REVISED APRIL 1999
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
CLK
1D
C1
CLK
B1
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
3
54
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
–0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, V
O
(see Note 1)
–0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, V
O
(see Note 1)
–0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . .
Current into any output in the low state, I
O
: SN54LVTH16501 96
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVTH16501 128
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
O
(see Note 2): SN54LVTH16501
48 mA
. . . . . . . . . . . . . . . . . . . . .
SN74LVTH16501 64
mA
. . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
–50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
–50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
θ
JA
(see Note 3): DGG package
81
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package
74
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700D – JULY 1997 – REVISED APRIL 1999
5
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
SN54LVTH16501
SN74LVTH16501
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
2.7
3.6
2.7
3.6
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
5.5
5.5
V
IOH
High-level output current
–24
–32
mA
IOL
Low-level output current
48
64
mA
∆
t/
∆
v
Input transition rise or fall rate
Outputs enabled
10
10
ns/V
∆
t/
∆
VCC
Power-up ramp rate
200
200
µ
s/V
TA
Operating free-air temperature
–55
125
–40
85
°
C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700D – JULY 1997 – REVISED APRIL 1999
6
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LVTH16501
SN74LVTH16501
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
MIN
TYP†
MAX
UNIT
VIK
VCC = 2.7 V,
II = –18 mA
–1.2
–1.2
V
VCC = 2.7 V to 3.6 V,
IOH = –100
µ
A
VCC–0.2
VCC–0.2
VOH
VCC = 2.7 V,
IOH = –8 mA
2.4
2.4
V
VOH
VCC = 3 V
IOH = –24 mA
2
V
VCC = 3 V
IOH = –32 mA
2
VCC = 2 7 V
IOL = 100
µ
A
0.2
0.2
VCC = 2.7 V
IOL = 24 mA
0.5
0.5
VOL
IOL = 16 mA
0.4
0.4
V
VOL
VCC = 3 V
IOL = 32 mA
0.5
0.5
V
VCC = 3 V
IOL = 48 mA
0.55
IOL = 64 mA
0.55
Control inputs
VCC = 3.6 V,
VI = VCC or GND
±
1
±
1
Control inputs
VCC = 0 or 3.6 V,
VI = 5.5 V
10
10
II
‡
VI = 5.5 V
20
20
µ
A
A or B ports‡
VCC = 3.6 V
VI = VCC
1
1
VI = 0
–5
–5
Ioff
VCC = 0,
VI or VO = 0 to 4.5 V
±
100
µ
A
VCC = 3 V
VI = 0.8 V
75
75
II(hold)
A or B ports
VCC = 3 V
VI = 2 V
–75
–75
µ
A
(
)
VCC = 3.6 V§,
VI = 0 to 3.6 V
±
500
IOZPU
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE/OE = don’t care
±
100*
±
100
µ
A
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE/OE = don’t care
±
100*
±
100
µ
A
VCC = 3.6 V,
Outputs high
0.19
0.19
ICC
VCC = 3.6 V,
IO = 0,
Outputs low
5
5
mA
VI = VCC or GND
Outputs disabled
0.19
0.19
∆
ICC¶
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
0.2
0.2
mA
Ci
VI = 3 V or 0
4
4
pF
Cio
VO = 3 V or 0
10
10
pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
† All typical values are at VCC = 3.3 V, TA = 25
°
C.
‡ Unused pins at VCC or GND
§ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700D – JULY 1997 – REVISED APRIL 1999
7
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH16501
SN74LVTH16501
VCC = 3.3 V
±
0.3 V
VCC = 2.7 V
VCC = 3.3 V
±
0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
150
150
150
150
MHz
t
Pulse duration
LE high
3.3
3.3
3.3
3.3
ns
tw
Pulse duration
CLK high or low
3.3
3.3
3.3
3.3
ns
A before CLKAB
↑
2.3
2.6
2.1
2.4
t
Setup time
B before CLKBA
↑
2.3
2.6
2.1
2.4
ns
tsu
Setup time
A or B before LE
↓
CLK high
2.6
1.8
2.4
1.6
ns
A or B before LE
↓
CLK low
1.6
0.7
1.4
0.5
th
Hold time
A or B after CLK
↑
1.1
0
1
0
ns
th
Hold time
A or B after LE
↓
1.8
1.8
1.7
1.7
ns
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVTH16501
SN74LVTH16501
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
±
0.3 V
VCC = 2.7 V
VCC = 3.3 V
±
0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
TYP†
MAX
MIN
MAX
fmax
150
150
150
150
MHz
tPLH
B or A
A or B
1.2
3.9
4.3
1.3
2.7
3.7
4
ns
tPHL
B or A
A or B
1.2
3.9
4.3
1.3
2.4
3.7
4
ns
tPLH
LEBA or LEAB
A or B
1.4
5.5
5.9
1.5
3.4
5.1
5.7
ns
tPHL
LEBA or LEAB
A or B
1.4
5.5
5.9
1.5
3.5
5.1
5.7
ns
tPLH
CLKBA or
A or B
1.2
5.4
6
1.3
3.5
5.1
5.7
ns
tPHL
CLKAB
A or B
1.2
5.4
6
1.3
3.4
5.1
5.7
ns
tPZH
OEBA or OEAB
A or B
1.2
5.1
5.8
1.3
3.4
4.8
5.5
ns
tPZL
OEBA or OEAB
A or B
1.2
5.1
5.8
1.3
3.4
4.8
5.5
ns
tPHZ
OEBA or OEAB
A or B
1.6
6.1
6.6
1.7
4.2
5.8
6.3
ns
tPLZ
OEBA or OEAB
A or B
1.6
6.1
6.6
1.7
3.8
5.8
6.3
ns
† All typical values are at VCC = 3.3 V, TA = 25
°
C.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700D – JULY 1997 – REVISED APRIL 1999
8
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500
Ω
500
Ω
Data Input
Timing Input
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
2.7 V
0 V
Input
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOL + 0.3 V
VOH – 0.3 V
≈
0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, ZO = 50
Ω
, tr
≤
2.5 ns, tf
≤
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
6 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
th
tsu
1.5 V
1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE<