background image
SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
1
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
™
Family
D
EPIC
™
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
UBT
™
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
D
B-Port Outputs Have Equivalent 26-
Ω
Series Resistors, So No External Resistors
Are Required
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR.
description
This 18-bit universal bus transceiver is designed
for 1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH162601 combines D-type
latches and D-type flip-flops to allow data flow in
transparent, latched, clocked, and clock-enabled
modes.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and
CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored
in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is low, the outputs are active. When
OEAB is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.
The B-port outputs include equivalent 26-
Ω
series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Copyright
©
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC, and UBT are trademarks of Texas Instruments Incorporated.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEAB
LEAB
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
OEBA
LEBA
CLKENAB
CLKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CLKBA
CLKENBA
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SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
description (continued)
The SN74ALVCH162601 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE†
INPUTS
OUTPUT
CLKENAB
OEAB
LEAB
CLKAB
A
B
X
H
X
X
X
Z
X
L
H
X
L
L
X
L
H
X
H
H
H
L
L
X
X
B0‡
H
L
L
X
X
B0‡
L
L
L
↑
L
L
L
L
L
↑
H
H
L
L
L
L or H
X
B0‡
† A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA,
LEBA, CLKBA, and CLKENBA.
‡ Output level before the indicated steady-state input conditions were
established
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SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
3
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
logic diagram (positive logic)
CE
1D
C1
CLK
CE
1D
C1
CLK
B1
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
A1
1
56
55
2
28
30
29
27
3
54
To 17 Other Channels
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SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
: Except I/O ports (see Note 1)
–0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports (see Notes 1 and 2)
–0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Notes 1 and 2)
–0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
–50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
–50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
±
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each V
CC
or GND
±
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
θ
JA
(see Note 3): DGG package
81
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package
74
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
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SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
5
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN
MAX
UNIT
VCC
Supply voltage
1.65
3.6
V
VCC = 1.65 V to 1.95 V
0.65
×
VCC
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
1.7
V
VCC = 2.7 V to 3.6 V
2
VCC = 1.65 V to 1.95 V
0.35
×
VCC
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
V
VCC = 2.7 V to 3.6 V
0.8
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 1.65 V
–4
High level output current (A port)
VCC = 2.3 V
–12
High-level output current (A port)
VCC = 2.7 V
–12
IOH
VCC = 3 V
–24
mA
IOH
VCC = 1.65 V
–2
mA
High level output current (B port)
VCC = 2.3 V
–6
High-level output current (B port)
VCC = 2.7 V
–8
VCC = 3 V
–12
VCC = 1.65 V
4
Low level output current (A port)
VCC = 2.3 V
12
Low-level output current (A port)
VCC = 2.7 V
12
IOL
VCC = 3 V
24
mA
IOL
VCC = 1.65 V
2
mA
Low level output current (B port)
VCC = 2.3 V
6
Low-level output current (B port)
VCC = 2.7 V
8
VCC = 3 V
12
∆
t/
∆
v
Input transition rise or fall rate
10
ns/V
TA
Operating free-air temperature
–40
85
°
C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
6
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP†
MAX
UNIT
IOH = –100
µ
A
1.65 V to 3.6 V
VCC–0.2
IOH = –4 mA
1.65 V
1.2
IOH = –6 mA
2.3 V
2
A port
2.3 V
1.7
IOH = –12 mA
2.7 V
2.2
3 V
2.4
VOH
IOH = –24 mA
3 V
2
V
VOH
IOH = –100
µ
A
1.65 V to 3.6 V
VCC–0.2
V
IOH = –2 mA
1.65 V
1.2
IOH = –4 mA
2.3 V
1.9
B port
IOH = 6 mA
2.3 V
1.7
IOH = –6 mA
3 V
2.4
IOH = –8 mA
2.7 V
2
IOH = –12 mA
3 V
2
IOL = 100
µ
A
1.65 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
A port
IOL = 6 mA
2.3 V
0.4
A port
IOL = 12 mA
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
3 V
0.55
VOL
IOL = 100
µ
A
1.65 V to 3.6 V
0.2
V
IOL = 2 mA
1.65 V
0.45
IOL = 4 mA
2.3 V
0.4
B port
IOL = 6 mA
2.3 V
0.55
IOL = 6 mA
3 V
0.55
IOL = 8 mA
2.7 V
0.6
IOL = 12 mA
3 V
0.8
II
VI = VCC or GND
3.6 V
±
5
µ
A
VI = 0.58 V
1 65 V
25
VI = 1.07 V
1.65 V
–25
VI = 0.7 V
2 3 V
45
II(hold)
VI = 1.7 V
2.3 V
–45
µ
A
(
)
VI = 0.8 V
3 V
75
VI = 2 V
3 V
–75
VI = 0 to 3.6 V‡
3.6 V
±
500
IOZ§
VO = VCC or GND
3.6 V
±
10
µ
A
ICC
VI = VCC or GND,
IO = 0
3.6 V
40
µ
A
∆
ICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
3 V to 3.6 V
750
µ
A
Ci
Control inputs
VI = VCC or GND
3.3 V
4
pF
Cio
A or B ports
VO = VCC or GND
3.3 V
8
pF
† All typical values are at VCC = 3.3 V, TA = 25
°
C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ For I/O ports, the parameter IOZ includes the input leakage current.
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SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
7
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
VCC = 1.8 V
VCC = 2.5 V
±
0.2 V
VCC = 2.7 V
VCC = 3.3 V
±
0.3 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
†
140
150
150
MHz
t
Pulse
LE high
†
3.3
3.3
3.3
ns
tw
duration
CLK high or low
†
3.3
3.3
3.3
ns
Data before CLK
↑
†
2.3
2.4
2.1
t
Setup time
Data before LE
↓
CLK high
†
2
1.6
1.6
ns
tsu
Setup time
Data before LE
↓
CLK low
†
1.3
1.2
1.1
ns
CLKEN before CLK
↑
†
2
2
1.7
Data after CLK
↑
†
0.7
0.7
0.8
th
Hold time
Data after LE
↓
CLK high
†
1.3
1.6
1.4
ns
th
Hold time
Data after LE
↓
CLK low
†
1.7
2
1.7
ns
CLKEN after CLK
↑
†
0.3
0.5
0.6
† This information was not available at the time of publication.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
VCC = 2.5 V
±
0.2 V
VCC = 2.7 V
VCC = 3.3 V
±
0.3 V
UNIT
(INPUT)
(OUTPUT)
MIN
TYP
MIN
MAX
MIN
MAX
MIN
MAX
fmax
†
140
150
150
MHz
A
B
†
1.3
4.8
5.2
1.6
4.5
B
A
†
1
4.3
4.6
1
4.1
t d
LEAB
B
†
1
5.5
5.9
1.5
5.1
ns
tpd
LEBA
A
†
1
5
5.3
1
4.7
ns
CLKAB
B
†
1.5
6.1
6.3
1.6
5.5
CLKBA
A
†
1.3
5.6
5.8
1.4
5
ten
OEAB
B
†
1.6
6.1
6.7
1.6
5.7
ns
tdis
OEAB
B
†
1.8
5.7
5.3
1.8
4.8
ns
ten
OEBA
A
†
1.1
5.5
6.1
1.1
5.2
ns
tdis
OEBA
A
†
1.3
5.2
4.8
1.6
4.4
ns
† This information was not available at the time of publication.
operating characteristics, T
A
= 25
°
C
PARAMETER
TEST CONDITIONS
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
UNIT
PARAMETER
TEST CONDITIONS
TYP
TYP
TYP
UNIT
C d
Power dissipation
Outputs enabled
CL = 50 pF
f = 10 MHz
†
41
50
pF
Cpd
capacitance
Outputs disabled
CL = 50 pF,
f = 10 MHz
†
6
6
pF
† This information was not available at the time of publication.
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SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
8
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 1.8 V
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
1 k
Ω
1 k
Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
×
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
VCC
0 V
0 V
tw
VCC
VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2
×
VCC
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, ZO = 50
Ω
, tr
≤
2 ns, tf
≤
2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2
VCC/2
VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
VCC/2
tPLH
2
×
VCC
VCC
Figure 1. Load Circuit and Voltage Waveforms
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SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
9
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.5 V
±
0.2 V
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500
Ω
500
Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
×
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
VCC
0 V
0 V
tw
VCC
VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2
×
VCC
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.