SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
1
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
™
Family
D
EPIC
™
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
DOC
™
(Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D
Dynamic Drive Capability Is Equivalent to
Standard Outputs With I
OH
and I
OL
of
±
24 mA at 2.5-V V
CC
D
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
D
I
off
Supports Partial-Power-Down Mode
Operation
D
Ideal for Use in PC133 Registered DIMM
Applications
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical V
OL
vs I
OL
and V
OH
vs I
OH
curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,
AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC
™
)
Circuitry Technology and Applications, literature number SCEA009.
136
–128
–144
–160
0.4
0.8
1.2
1.6
2.0
2.4
2.8
170
153
119
102
85
68
51
34
17
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
TA = 25
°
C
Process = Nominal
IOL – Output Current – mA
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
– Output V
oltage – V
OL
V
TA = 25
°
C
Process = Nominal
IOH – Output Current – mA
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
– Output V
oltage – V
OH
V
–80
–96
–112
–32
–48
–64
0
–16
Figure 1. Output Voltage vs Output Current
This 16-bit universal bus driver is operational at 1.2-V to 3.6-V V
CC
, but is designed specifically for 1.65-V to
3.6-V V
CC
operation.
Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode
when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held
at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition
of CLK. When OE is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Copyright
©
2000, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
description (continued)
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16334 is characterized for operation from –40
°
C to 85
°
C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OE
Y1
Y2
GND
Y3
Y4
V
CC
Y5
Y6
GND
Y7
Y8
Y9
Y10
GND
Y11
Y12
V
CC
Y13
Y14
GND
Y15
Y16
NC
CLK
A1
A2
GND
A3
A4
V
CC
A5
A6
GND
A7
A8
A9
A10
GND
A11
A12
V
CC
A13
A14
GND
A15
A16
LE
NC – No internal connection
FUNCTION TABLE
(each universal bus driver)
INPUTS
OUTPUT
OE
LE
CLK
A
Y
H
X
X
X
Z
L
L
X
L
L
L
L
X
H
H
L
H
↑
L
L
L
H
↑
H
H
L
H
L or H
X
Y0†
† Output level before the indicated steady-state
input conditions were established
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
3
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
logic symbol
†
1
6
Y4
A1
47
3D
A2
46
A3
44
A4
43
A5
41
A6
40
A7
38
A8
37
A9
36
A10
35
A11
33
A12
32
A13
30
A14
29
A15
27
A16
26
OE
EN1
1
48
CLK
1
2
Y1
3
Y2
5
Y3
8
Y5
9
Y6
11
Y7
12
Y8
13
Y9
14
Y10
16
Y11
17
Y12
19
Y13
20
Y14
22
Y15
23
Y16
C3
25
G2
LE
2C3
1
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
48
25
47
1D
C1
CLK
2
To 15 Other Channels
OE
CLK
LE
A1
Y1
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
–0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1)
–0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2)
–0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
–50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
–50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
±
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each V
CC
or GND
±
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
θ
JA
(see Note 3): DGG package
70
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
58
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
5
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN
MAX
UNIT
VCC
Supply voltage
Operating
1.4
3.6
V
VCC
Supply voltage
Data retention only
1.2
V
VCC = 1.2 V
VCC
VCC = 1.4 V to 1.6 V
0.65
×
VCC
VIH
High-level input voltage
VCC = 1.65 V to 1.95 V
0.65
×
VCC
V
VCC = 2.3 V to 2.7 V
1.7
VCC = 3 V to 3.6 V
2
VCC = 1.2 V
GND
VCC = 1.4 V to 1.6 V
0.35
×
VCC
VIL
Low-level input voltage
VCC = 1.65 V to 1.95 V
0.35
×
VCC
V
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VI
Input voltage
0
3.6
V
VO
Output voltage
Active state
0
VCC
V
VO
Output voltage
3-state
0
3.6
V
†
VCC = 1.4 V to 1.6 V
–2
IOHS
Static high level output current†
VCC = 1.65 V to 1.95 V
–4
mA
IOHS
Static high-level output current†
VCC = 2.3 V to 2.7 V
–8
mA
VCC = 3 V to 3.6 V
–12
†
VCC = 1.4 V to 1.6 V
2
IOLS
Static low level output current†
VCC = 1.65 V to 1.95 V
4
mA
IOLS
Static low-level output current†
VCC = 2.3 V to 2.7 V
8
mA
VCC = 3 V to 3.6 V
12
∆
t/
∆
v
Input transition rise or fall rate
VCC = 1.4 V to 3.6 V
5
ns/V
TA
Operating free-air temperature
–40
85
°
C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of
±
24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH
characteristics. Refer to the TI application reports,
AVC Logic Family Technology and Applications, literature number SCEA006, and
Dynamic Output Control (DOC
™
) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
6
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP†
MAX
UNIT
IOHS = –100
µ
A
1.4 V to 3.6 V
VCC–0.2
IOHS = –2 mA,
VIH = 0.91 V
1.4 V
1.05
VOH
IOHS = –4 mA,
VIH = 1.07 V
1.65 V
1.2
V
IOHS = –8 mA,
VIH = 1.7 V
2.3 V
1.75
IOHS = –12 mA,
VIH = 2 V
3 V
2.3
IOLS = 100
µ
A
1.4 V to 3.6 V
0.2
IOLS = 2 mA,
VIL = 0.49 V
1.4 V
0.4
VOL
IOLS = 4 mA,
VIL = 0.57 V
1.65 V
0.45
V
IOLS = 8 mA,
VIL = 0.7 V
2.3 V
0.55
IOLS = 12 mA,
VIL = 0.8 V
3 V
0.7
II
Control inputs
VI = VCC or GND
3.6 V
±
2.5
µ
A
Ioff
VI or VO = 3.6 V
0
±
10
µ
A
IOZ
VO = VCC or GND
3.6 V
±
10
µ
A
ICC
VI = VCC or GND,
IO = 0
3.6 V
40
µ
A
CLK input
VI = VCC or GND
2.5 V
4
CLK input
VI = VCC or GND
3.3 V
4
Ci
Control inputs
VI = VCC or GND
2.5 V
4
pF
Ci
Control inputs
VI = VCC or GND
3.3 V
4
pF
Data inputs
VI = VCC or GND
2.5 V
2.5
Data inputs
VI = VCC or GND
3.3 V
2.5
Co
Outputs
VO = VCC or GND
2.5 V
6.5
pF
Co
Out uts
VO = VCC or GND
3.3 V
6.5
F
† Typical values are measured at TA = 25
°
C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
VCC = 1.5 V
±
0.1 V
VCC = 1.8 V
±
0.15 V
VCC = 2.5 V
±
0.2 V
VCC = 3.3 V
±
0.3 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
150
150
150
MHz
t
Pulse
LE low
3.3
3.3
3.3
ns
tw
duration
CLK high or low
3.3
3.3
3.3
ns
S t
Data before CLK
↑
1
0.8
0.7
0.7
0.7
tsu
Setup
time
Data
CLK high
1.5
1.4
0.9
0.9
0.9
ns
time
before LE
↑
CLK low
2.7
1.6
1.2
1
1
th
Hold
time
Data after CLK
↑
1.3
1.1
0.9
0.8
0.7
ns
th
Hold
Data
↑
CLK high
2.2
1.9
1.7
1.5
1.5
ns
th
time
after LE
↑
CLK low
2.4
1.8
1.6
1.4
1.3
ns
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
7
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.2 V
VCC = 1.5 V
±
0.1 V
VCC = 1.8 V
±
0.15 V
VCC = 2.5 V
±
0.2 V
VCC = 3.3 V
±
0.3 V
UNIT
(INPUT)
(OUTPUT)
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fmax
150
150
150
MHz
A
5.3
1.2
6.2
1.5
4.9
1
3.2
0.9
2.5
tpd
LE
Y
7
2.2
9.7
1.8
7.5
1.5
4.9
0.8
4
ns
CLK
6
1.9
7.8
1.6
6
1.1
3.7
1
3.1
ten
OE
Y
7.9
2.4
10.2
1.6
8.8
1.5
6.7
1
6.2
ns
tdis
OE
Y
7.7
2.1
10.3
1.5
8.4
1.2
5.3
1
5.3
ns
switching characteristics, T
A
= 0
°
C to 85
°
C, C
L
= 0 pF
†
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
±
0.15 V
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
tpd
A
Y
0.6
1.3
ns
tpd
CLK
Y
0.7
1.5
ns
† Texas Instruments SPICE simulation data
operating characteristics, T
A
= 25
°
C
PARAMETER
TEST CONDITIONS
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
UNIT
PARAMETER
TEST CONDITIONS
TYP
TYP
TYP
UNIT
C d
Power dissipation
Outputs enabled
CL = 0
f = 10 MHz
45
48
52
pF
Cpd
capacitance
Outputs disabled
CL = 0,
f = 10 MHz
23
25
28
pF
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
8
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 1.2 V AND 1.5 V
±
0.1 V
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 15 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
2 k
Ω
2 k
Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
×
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.1 V
VOH – 0.1 V
0 V
VCC
0 V
0 V
tw
VCC
VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2
×
VCC
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, ZO = 50
Ω
, tr
≤
2 ns, tf
≤
2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2
VCC/2
VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2