20-Bit Universal Bus Driver With 3-State Outputs

SN74ALVCH162836

20-BIT UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCES122E – JULY 1997 – REVISED JUNE 1999

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

Member of the Texas Instruments

Widebus

™

Family

EPIC

™

(Enhanced-Performance Implanted

CMOS) Submicron Process

Output Port Has Equivalent 26-

Ω

Series

Resistors, So No External Resistors Are

Required

Designed to Comply With JEDEC 168-Pin

and 200-Pin SDRAM Buffered DIMM

Specification

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Latch-Up Performance Exceeds 250 mA Per

JESD 17

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

Package Options Include Plastic Shrink

Small-Outline (DL), Thin Shrink

Small-Outline (DGG), and Thin Very

Small-Outline (DGV) Packages

NOTE: For tape and reel order entry:

The DGGR package is abbreviated to GR, and

the DGVR package is abbreviated to VR.

description

This 20-bit universal bus driver is designed for

1.65-V to 3.6-V V

operation.

Data flow from A to Y is controlled by the

output-enable (OE) input. The device operates in

the transparent mode when the latch-enable (LE)

input is low. When LE is high, the A data is latched

if the clock (CLK) input is held at a high or low logic

level. If LE is high, the A data is stored in the

latch/flip-flop on the low-to-high transition of CLK.

When OE is high, the outputs are in the

high-impedance state.

The output port includes equivalent 26-

Ω

series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH162836 is characterized for operation from –40

C to 85

1999, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DGG, DGV, OR DL PACKAGE

(TOP VIEW)

GND

Y10

Y11

Y12

Y13

GND

Y14

Y15

Y16

Y17

Y18

GND

Y19

Y20

CLK

GND

A10

A11

A12

A13

GND

A14

A15

A16

A17

A18

GND

A19

A20

NC – No internal connection

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

SN74ALVCH162836

20-BIT UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCES122E – JULY 1997 – REVISED JUNE 1999

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

FUNCTION TABLE

INPUTS

OUTPUT

CLK

↑

L or H

Y0†

† Output level before the indicated steady-state

input conditions were established

logic symbol

‡

A10

A11

A12

A13

A14

A15

A16

A17

A18

EN1

CLK

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

2C3

A19

A20

Y19

Y20

‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

SN74ALVCH162836

20-BIT UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCES122E – JULY 1997 – REVISED JUNE 1999

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

logic diagram (positive logic)

CLK

To 19 Other Channels

CLK

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

–0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(see Note 1)

–0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

(see Notes 1 and 2)

–0.5 V to V

+ 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

< 0)

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

< 0)

–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through each V

or GND

100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance,

(see Note 3): DGG package

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

SN74ALVCH162836

20-BIT UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCES122E – JULY 1997 – REVISED JUNE 1999

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

recommended operating conditions (see Note 4)

MIN

MAX

UNIT

VCC

Supply voltage

1.65

3.6

VCC = 1.65 V to 1.95 V

0.65

VCC

VIH

High-level input voltage

VCC = 2.3 V to 2.7 V

1.7

VCC = 2.7 V to 3.6 V

VCC = 1.65 V to 1.95 V

0.35

VCC

VIL

Low-level input voltage

VCC = 2.3 V to 2.7 V

0.7

VCC = 2.7 V to 3.6 V

0.8

Input voltage

VCC

Output voltage

VCC

VCC = 1.65 V

–2

IOH

High level output current

VCC = 2.3 V

–6

IOH

High-level output current

VCC = 2.7 V

–8

VCC = 3 V

–12

VCC = 1.65 V

IOL

Low level output current

VCC = 2.3 V

IOL

Low-level output current

VCC = 2.7 V

VCC = 3 V

∆

Input transition rise or fall rate

ns/V

Operating free-air temperature

–40

NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

SN74ALVCH162836

20-BIT UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCES122E – JULY 1997 – REVISED JUNE 1999

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP†

MAX

UNIT

IOH = –100

1.65 V to 3.6 V

VCC–0.2

IOH = –2 mA

1.65 V

1.2

IOH = –4 mA

2.3 V

1.9

VOH

IOH = 6 mA

2.3 V

1.7

IOH = –6 mA

3 V

2.4

IOH = –8 mA

2.7 V

IOH = –12 mA

3 V

IOL = 100

1.65 V to 3.6 V

0.2

IOL = 2 mA

1.65 V

0.45

IOL = 4 mA

2.3 V

0.4

VOL

IOL = 6 mA

2.3 V

0.55

IOL = 6 mA

3 V

0.55

IOL = 8 mA

2.7 V

0.6

IOL = 12 mA

3 V

0.8

VI = VCC or GND

3.6 V

VI = 0.58 V

1.65 V

VI = 1.07 V

1.65 V

–25

VI = 0.7 V

2.3 V

II(hold)

VI = 1.7 V

2.3 V

–45

(

)

VI = 0.8 V

3 V

VI = 2 V

3 V

–75

VI = 0 to 3.6 V‡

3.6 V

500

IOZ

VO = VCC or GND

3.6 V

ICC

VI = VCC or GND,

IO = 0

3.6 V

∆

ICC

One input at VCC – 0.6 V,

Other inputs at VCC or GND

3 V to 3.6 V

750

Control inputs

VI = VCC or GND

3 3 V

5.5

Data inputs

VI = VCC or GND

3.3 V

Outputs

VO = VCC or GND

3.3 V

† All typical values are at VCC = 3.3 V, TA = 25

‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

SN74ALVCH162836

20-BIT UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCES122E – JULY 1997 – REVISED JUNE 1999

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figures 1 through 3)

VCC = 1.8 V

VCC = 2.5 V

0.2 V

VCC = 2.7 V

VCC = 3.3 V

0.3 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

†

150

MHz

Pulse duration

LE low

†

3.3

Pulse duration

CLK high or low

†

3.3

Data before CLK

↑

†

1.4

1.7

1.5

tsu

Setup time

Data before LE

↑

CLK high

†

1.2

1.6

1.3

Data before LE

↑

CLK low

†

1.4

1.5

1.2

Data after CLK

↑

†

0.9

Hold time

Data after LE

↑

CLK

high or low

†

1.1

† This information was not available at the time of publication.

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figures 1 through 3)

PARAMETER

FROM

(INPUT)

(OUTPUT)

VCC = 1.8 V

VCC = 2.5 V

0.2 V

VCC = 2.7 V

VCC = 3.3 V

0.3 V

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MIN

MAX

MIN

MAX

MIN

MAX

fmax

†

150

MHz

†

4.4

4.6

1.2

tpd

†

1.1

5.8

6.1

1.4

5.1

CLK

†

5.2

5.5

1.1

ten

†

1.1

6.4

6.5

1.2

5.5

tdis

†

4.7

5.2

1.7

5.1

† This information was not available at the time of publication.

operating characteristics, T

= 25

PARAMETER

TEST CONDITIONS

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V

UNIT

PARAMETER

TEST CONDITIONS

TYP

UNIT

C d

Power dissipation

Outputs enabled

CL = 0

f = 10 MHz

†

31.5

Cpd

capacitance

Outputs disabled

CL = 0,

f = 10 MHz

†

10.5

† This information was not available at the time of publication.

SN74ALVCH162836

20-BIT UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCES122E – JULY 1997 – REVISED JUNE 1999

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

= 1.8 V

VCC/2

VOH

VOL

tsu

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

Open

GND

1 k

Ω

1 k

Ω

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2

VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

VCC

0 V

VCC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

VCC

GND

TEST

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤

10 MHz, ZO = 50

Ω

, tr

≤

2 ns, tf

≤

2 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

0 V

VCC

VCC/2

tPHL

VCC/2

VCC

0 V

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2

tPLH

VCC

Figure 1. Load Circuit and Voltage Waveforms

SN74ALVCH162836

20-BIT UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCES122E – JULY 1997 – REVISED JUNE 1999

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

= 2.5 V

0.2 V

VCC/2

VOH

VOL

tsu

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

Open

GND

500

Ω

500

Ω

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2

VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

VCC

0 V

VCC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

VCC

GND

TEST

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤

10 MHz, ZO = 50

Ω

, tr

≤

2 ns, tf

≤

2 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

0 V

VCC

VCC/2

tPHL

VCC/2

VCC

0 V

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2

tPLH

VCC

Figure 2. Load Circuit and Voltage Waveforms