SN54LVT245B, SN74LVT245B
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES004D – JANUARY 1995 – REVISED APRIL 2000
1
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
CC
)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
D
I
off
and Power-Up 3-State Support Hot
Insertion
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Packages, and Ceramic
(J) DIPs
description
These octal bus transceivers are designed
specifically for low-voltage (3.3-V) V
CC
operation,
but with the capability to provide a TTL interface
to a 5-V system environment.
These devices are designed for asynchronous communication between data buses. They transmit data from
the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the devices so the buses are effectively isolated.
When V
CC
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
CC
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVT245B is characterized for operation over the full military temperature range of –55
°
C to 125
°
C.
The SN74LVT245B is characterized for operation from –40
°
C to 85
°
C.
Copyright
©
2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LVT245B . . . J OR W PACKAGE
SN74LVT245B . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
SN54LVT245B . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
B1
B2
B3
B4
B5
A3
A4
A5
A6
A7
A2
A1
DIR
B7
B6
OE
A8
GND
B8
V
CC
SN54LVT245B, SN74LVT245B
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES004D – JANUARY 1995 – REVISED APRIL 2000
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OPERATION
OE
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
logic symbol
†
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
B2
17
B3
16
B4
15
A5
6
A6
7
A7
8
A8
9
A2
3
A3
4
A4
5
OE
A1
2
G3
19
3EN2[AB]
B5
14
B6
13
B7
12
B8
11
B1
18
3EN1[BA]
1
DIR
1
2
logic diagram (positive logic)
DIR
OE
A1
B1
To Seven Other Channels
1
2
19
18
SN54LVT245B, SN74LVT245B
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES004D – JANUARY 1995 – REVISED APRIL 2000
3
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
–0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, V
O
(see Note 1)
–0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, V
O
(see Note 1)
–0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . .
Current into any output in the low state, I
O
: SN54LVT245B 96
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVT245B
128 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
O
(see Note 2): SN54LVT245B
48 mA
. . . . . . . . . . . . . . . . . . . . . . . .
SN74LVT245B
64 mA
. . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
–50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
–50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
θ
JA
(see Note 3): DB package
70
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
58
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
83
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVT245B
SN74LVT245B
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
2.7
3.6
2.7
3.6
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
5.5
5.5
V
IOH
High-level output current
–24
–32
mA
IOL
Low-level output current
48
64
mA
∆
t/
∆
v
Input transition rise or fall rate
Outputs enabled
10
10
ns/V
∆
t/
∆
VCC
Power-up ramp rate
200
200
µ
s/V
TA
Operating free-air temperature
–55
125
–40
85
°
C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVT245B, SN74LVT245B
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES004D – JANUARY 1995 – REVISED APRIL 2000
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LVT245B
SN74LVT245B
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
MIN
TYP†
MAX
UNIT
VIK
VCC = 2.7 V,
II = –18 mA
–1.2
–1.2
V
VCC = 2.7 V to 3.6 V,
IOH = –100
µ
A
VCC–0.2
VCC–0.2
VOH
VCC = 2.7 V,
IOH = –8 mA
2.4
2.4
V
VOH
VCC = 3 V
IOH = –24 mA
2
V
VCC = 3 V
IOH = –32 mA
2
VCC = 2 7 V
IOL = 100
µ
A
0.2
0.2
VCC = 2.7 V
IOL = 24 mA
0.5
0.5
VOL
IOL = 16 mA
0.4
0.4
V
VOL
VCC = 3 V
IOL = 32 mA
0.5
0.5
V
VCC = 3 V
IOL = 48 mA
0.55
IOL = 64 mA
0.55
Control inputs
VCC = 3.6 V,
VI = VCC or GND
±
1
±
1
Control inputs
VCC = 0 or 3.6 V,
VI = 5.5 V
10
10
II
‡
VI = 5.5 V
20
20
µ
A
A or B ports‡
VCC = 3.6 V
VI = VCC
1
1
VI = 0
–5
–5
Ioff
VCC = 0,
VI or VO = 0 to 4.5 V
±
100
µ
A
IOZH
VCC = 3.6 V,
VO = 3 V
5
5
µ
A
IOZL
VCC = 3.6 V,
VO = 0.5 V
–5
–5
µ
A
IOZPU
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don’t care
±
100
∗
±
100
µ
A
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don’t care
±
100
∗
±
100
µ
A
VCC = 3.6 V,
Outputs high
0.19
0.19
ICC
VCC = 3.6 V,
IO = 0,
Outputs low
5
5
mA
VI = VCC or GND
Outputs disabled
0.19
0.19
∆
ICC§
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
0.2
0.2
mA
Ci
VI = 3 V or 0
4
4
pF
Cio
VO = 3 V or 0
9
9
pF
∗
On products compliant to MIL-PRF-38535, this parameter is not production tested.
† All typical values are at VCC = 3.3 V, TA = 25
°
C.
‡ Unused terminals are at VCC or GND.
§ This is the increase in supply current for each input that is at the specified TTL-voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVT245B, SN74LVT245B
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES004D – JANUARY 1995 – REVISED APRIL 2000
5
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVT245B
SN74LVT245B
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
±
0.3 V
VCC = 2.7 V
VCC = 3.3 V
±
0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
TYP†
MAX
MIN
MAX
tPLH
A or B
B or A
1.1
3.7
4.2
1.2
2.3
3.5
4
ns
tPHL
A or B
B or A
1.1
3.7
4.2
1.2
2.1
3.5
4
ns
tPZH
OE
A or B
1.2
5.7
7.4
1.3
3.2
5.5
7.1
ns
tPZL
OE
A or B
1.6
5.7
6.8
1.7
3.4
5.5
6.5
ns
tPHZ
OE
A or B
2.1
6.2
6.8
2.2
3.5
5.9
6.5
ns
tPLZ
OE
A or B
2.1
5.3
5.5
2.2
3.4
5
5.1
ns
† All typical values are at VCC = 3.3 V, TA = 25
°
C.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVT245B, SN74LVT245B
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES004D – JANUARY 1995 – REVISED APRIL 2000
6
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
6 V
Open
GND
500
Ω
500
Ω
Data Input
Timing Input
1.5 V
2.7 V
0 V
1.5 V
1.5 V
2.7 V
0 V
2.7 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
2.7 V
0 V
1.5 V
1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
3 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
≈
0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, ZO = 50
Ω
, tr
≤
2.5 ns, tf
≤
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright
©
2000, Texas Instruments Incorporated