12C5X_GEBook

1998 Microchip Technology Inc.

DS40139D-page 1

Devices included in this Data Sheet:

• PIC12C508

• PIC12C508A

• PIC12C509

• PIC12C509A

Note:

Throughout this data sheet PIC12C508(A)

refers to the PIC12C508 and PIC12C508A.

PIC12C509(A) refers to the PIC12C509

and PIC12C509A. PIC12C5XX refers to

the PIC12C508, PIC12C508A, PIC12C509

and PIC12C509A.

High-Performance RISC CPU:

• Only 33 single word instructions to learn

• All instructions are single cycle (1

s) except for

program branches which are two-cycle

• Operating speed: DC - 4 MHz clock input

DC - 1

s instruction cycle

• 12-bit wide instructions

• 8-bit wide data path

• Seven special function hardware registers

• Two-level deep hardware stack

• Direct, indirect and relative addressing modes for

data and instructions

• Internal 4 MHz RC oscillator with programmable

calibration

• In-circuit serial programming

Peripheral Features:

• 8-bit real time clock/counter (TMR0) with 8-bit

programmable prescaler

• Power-On Reset (POR)

• Device Reset Timer (DRT)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Programmable code-protection

• Power saving SLEEP mode

• Wake-up from SLEEP on pin change

• Internal weak pull-ups on I/O pins

• Internal pull-up on MCLR pin

• Selectable oscillator options:

- INTRC: Internal 4 MHz RC oscillator

Device

EPROM

RAM

PIC12C508

512 x 12

PIC12C508A

512 x 12

PIC12C509

1024 x 12

PIC12C509A

1024 x 12

- EXTRC: External low-cost RC oscillator

- XT:

Standard crystal/resonator

- LP:

Power saving, low frequency crystal

CMOS Technology:

• Low power, high speed CMOS EPROM

technology

• Fully static design

• Wide operating voltage range

• Wide temperature range:

- Commercial: 0

C to +70

- Industrial: -40

C to +85

- Extended: -40

C to +125

• Low power consumption

- < 2 mA @ 5V, 4 MHz

- 15

A typical @ 3V, 32 KHz

- < 1

A typical standby current

Pin Diagram

PDIP, SOIC, Windowed Ceramic Side Brazed

PIC12C508(A

)

GP0

GP1

GP2/T0CKI

PIC12C509(A)

GP5/OSC1/CLKIN

GP4/OSC2

GP3/MCLR/V

VDD

PIC12C5XX

8-Pin, 8-Bit CMOS Microcontroller

PIC12C5XX

DS40139D-page 2

1998 Microchip Technology Inc.

Device Differences

Note 1:

If you change from the PIC12C50X to the PIC12C50XA, please verify oscillator characteristics in your appli-

cation.

Note 2:

See Section 7.2.5 for OSCCAL implementation differences.

Device

Voltage

Range

Oscillator

Calibration

(Bits)

Process

Technology

(Microns)

PIC12C508A

3.0-5.5

See Note 1

0.7

PIC12LC508A

2.5-5.5

See Note 1

0.7

PIC12C508

2.5-5.5

See Note 1

0.9

PIC12C509A

3.0-5.5

See Note 1

0.7

PIC12LC509A

2.5-5.5

See Note 1

0.7

PIC12C509

2.5-5.5

See Note 1

0.9

PIC12C5XX

DS40139D-page 4

1998 Microchip Technology Inc.

1.0

GENERAL DESCRIPTION

The PIC12C5XX from Microchip Technology is a family

of low-cost, high performance, 8-bit, fully static,

EPROM/ROM-based CMOS microcontrollers.

employs a RISC architecture with only 33 single word/

single cycle instructions. All instructions are single

cycle (1

s) except for program branches which take

two cycles. The PIC12C5XX delivers performance an

order of magnitude higher than its competitors in the

same price category. The 12-bit wide instructions are

highly symmetrical resulting in 2:1 code compression

over other 8-bit microcontrollers in its class. The easy

to use and easy to remember instruction set reduces

development time signiﬁcantly.

The PIC12C5XX products are equipped with special

features that reduce system cost and power require-

ments. The Power-On Reset (POR) and Device Reset

Timer (DRT) eliminate the need for external reset cir-

cuitry. There are four oscillator conﬁgurations to choose

from, including INTRC internal oscillator mode and the

power-saving LP (Low Power) oscillator mode. Power

saving SLEEP mode, Watchdog Timer and code

protection features also improve system cost, power

and reliability.

The PIC12C5XX are available in the cost-effective

One-Time-Programmable (OTP) versions which are

suitable for production in any volume. The customer

can take full advantage of Microchip’s price leadership

in OTP microcontrollers while beneﬁting from the OTP’s

ﬂexibility.

The PIC12C5XX products are supported by a full-fea-

tured macro assembler, a software simulator, an in-cir-

cuit emulator, a ‘C’ compiler, fuzzy logic support tools,

a low-cost development programmer, and a full fea-

tured programmer. All the tools are supported on IBM

PC and compatible machines.

1.1

Applications

The PIC12C5XX series ﬁts perfectly in applications

ranging from personal care appliances and security

systems to low-power remote transmitters/receivers.

The EPROM technology makes customizing applica-

tion programs (transmitter codes, appliance settings,

receiver frequencies, etc.) extremely fast and conve-

nient. The small footprint packages, for through hole or

surface mounting, make this microcontroller series per-

fect for applications with space limitations. Low-cost,

low-power, high performance, ease of use and I/O ﬂex-

ibility make the PIC12C5XX series very versatile even

in areas where no microcontroller use has been

considered before (e.g., timer functions, replacement

of “glue” logic and PLD’s in larger systems, coproces-

sor applications).

1998 Microchip Technology Inc.

DS40139D-page 5

PIC12C5XX

TABLE 1-1:

PIC12CXXX & PIC12CEXXX FAMILY OF DEVICES

PIC12C508(A) PIC12C509(A) PIC12CE518 PIC12CE519

PIC12C671

PIC12C672 PIC12CE673 PIC12CE674

Clock

Maximum

Frequency

of Operation

(MHz)

Memory

EPROM

Program

Memory

512 x 12

1024 x 12

512 x 12

1024 x 12

1024 x 14

2048 x 14

1024 x 14

2048 x 14

RAM Data

Memory

(bytes)

128

Peripherals

EEPROM

Data Memory

(bytes)

—

Timer

Module(s)

TMR0

A/D Con-

verter (8-bit)

Channels

—

Features

Wake-up

from SLEEP

on pin

change

Yes

Interrupt

Sources

—

I/O Pins

Input Pins

Internal

Pull-ups

Yes

In-Circuit

Serial

Programming

Yes

Number of

Instructions

Packages

8-pin DIP,

JW, SOIC

8-pin DIP,

JW, SOIC

8-pin DIP,

JW, SOIC

8-pin DIP,

JW, SOIC

8-pin DIP,

JW, SOIC

8-pin DIP,

JW, SOIC

8-pin DIP,

All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable

code protect and high I/O current capability.

All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GP0 and clock pin GP1.

1998 Microchip Technology Inc.

DS40139D-page 7

PIC12C5XX

2.0

PIC12C5XX DEVICE VARIETIES

A variety of packaging options are available.

Depending on application and production

requirements, the proper device option can be

selected using the information in this section. When

placing orders, please use the PIC12C5XX Product

Identiﬁcation System at the back of this data sheet to

specify the correct part number.

2.1

UV Erasable Devices

The UV erasable version, offered in ceramic side

brazed package, is optimal for prototype development

and pilot programs.

The UV erasable version can be erased and

reprogrammed to any of the conﬁguration modes.

Microchip's PICSTART

PLUS and PRO MATE

pro-

grammers all support programming of the PIC12C5XX.

Third party programmers also are available; refer to the

Microchip

Third Party Guide

for a list of sources.

2.2

One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for

customers who need the ﬂexibility for frequent code

updates or small volume applications.

The OTP devices, packaged in plastic packages permit

the user to program them once. In addition to the

program memory, the conﬁguration bits must also be

programmed.

Note:

Please note that erasing the device will

also erase the pre-programmed internal

calibration value for the internal oscillator.

The calibration value must be saved prior

to erasing the part.

2.3

Quick-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for

factory production orders. This service is made

available for users who choose not to program a

medium to high quantity of units and whose code

patterns have stabilized. The devices are identical to

the OTP devices but with all EPROM locations and fuse

options already programmed by the factory. Certain

code and prototype veriﬁcation procedures do apply

before production shipments are available. Please con-

tact your local Microchip Technology sales ofﬁce for

more details.

2.4

Serialized Quick-Turnaround

Production (SQTP

) Devices

Microchip offers a unique programming service where

a few user-deﬁned locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password or ID number.

1998 Microchip Technology Inc.

DS40139D-page 9

PIC12C5XX

3.0

ARCHITECTURAL OVERVIEW

The high performance of the PIC12C5XX family can

be attributed to a number of architectural features

commonly found in RISC microprocessors. To begin

with, the PIC12C5XX uses a Harvard architecture in

which program and data are accessed on separate

buses. This improves bandwidth over traditional von

Neumann architecture where program and data are

fetched on the same bus. Separating program and

data memory further allows instructions to be sized

differently than the 8-bit wide data word. Instruction

opcodes are 12-bits wide making it possible to have all

single word instructions. A 12-bit wide program

memory access bus fetches a 12-bit instruction in a

single cycle. A two-stage pipeline overlaps fetch and

execution of instructions. Consequently, all instructions

(33) execute in a single cycle (1

s @ 4MHz) except for

program branches.

The table below lists program memory (EPROM) and

data memory (RAM) for each PIC12C5XX device.

The PIC12C5XX can directly or indirectly address its

registers including the program counter are mapped in

the data memory. The PIC12C5XX has a highly

orthogonal (symmetrical) instruction set that makes it

possible to carry out any operation on any register

using any addressing mode. This symmetrical nature

and lack of ‘special optimal situations’ make

programming with the PIC12C5XX simple yet efﬁcient.

In addition, the learning curve is reduced signiﬁcantly.

Device

EPROM

RAM

PIC12C508

512 x 12

PIC12C508A

512 x 12

PIC12C509

1024 x 12

PIC12C509A

1024 x 12

The PIC12C5XX device contains an 8-bit ALU and

working register. The ALU is a general purpose

arithmetic unit. It performs arithmetic and Boolean

functions between data in the working register and any

The ALU is 8-bits wide and capable of addition,

subtraction, shift and logical operations. Unless

otherwise mentioned, arithmetic operations are two's

complement in nature. In two-operand instructions,

typically one operand is the W (working) register. The

other operand is either a ﬁle register or an immediate

constant. In single operand instructions, the operand

is either the W register or a ﬁle register.

The W register is an 8-bit working register used for

ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC),

and Zero (Z) bits in the STATUS register. The C and

DC bits operate as a borrow and digit borrow out bit,

respectively, in subtraction. See the

SUBWF

and

ADDWF

instructions for examples.

A simpliﬁed block diagram is shown in Figure 3-1, with

the corresponding device pins described in Table 3-1.

PIC12C5XX

DS40139D-page 10

1998 Microchip Technology Inc.

FIGURE 3-1:

PIC12C5XX BLOCK DIAGRAM

Device Reset

Timer

Power-on

Reset

Watchdog

Timer

EPROM

Program

Memory

Data Bus

Program

Bus

Instruction reg

Program Counter

RAM

File

Registers

Direct Addr

RAM Addr

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2

MCLR

Vdd, Vss

Timer0

GPIO

GP4/OSC2

GP3/MCLR/Vpp

GP2/T0CKI

GP1

GP0

5-7

GP5/OSC1/CLKIN

STACK1

STACK2

512 x 12 or

25 x 8 or

1024 x 12

41 x 8

Internal RC

OSC

1998 Microchip Technology Inc.

DS40139D-page 11

PIC12C5XX

TABLE 3-1:

PIC12C5XX PINOUT DESCRIPTION

Name

DIP

Pin #

SOIC

Pin #

I/O/P

Type

Buffer

Type

Description

GP0

I/O

TTL/ST Bi-directional I/O port/ serial programming data. Can

be software programmed for internal weak pull-up and

wake-up from SLEEP on pin change. This buffer is a

Schmitt Trigger input when used in serial programming

mode.

GP1

I/O

TTL/ST Bi-directional I/O port/ serial programming clock. Can

be software programmed for internal weak pull-up and

wake-up from SLEEP on pin change. This buffer is a

Schmitt Trigger input when used in serial programming

mode.

GP2/T0CKI

I/O

Bi-directional I/O port. Can be conﬁgured as T0CKI.

GP3/MCLR/V

TTL/ST Input port/master clear (reset) input/programming volt-

age input. When conﬁgured as MCLR, this pin is an

active low reset to the device. Voltage on MCLR/V

must not exceed V

during normal device operation

or the device will enter programming mode. Can be

software programmed for internal weak pull-up and

wake-up from SLEEP on pin change. Weak pull-up

always on if conﬁgured as MCLR. ST when in MCLR

mode.

GP4/OSC2

I/O

TTL

Bi-directional I/O port/oscillator crystal output. Con-

nections to crystal or resonator in crystal oscillator

mode (XT and LP modes only, GPIO in other modes).

GP5/OSC1/CLKIN

I/O

TTL/ST Bidirectional IO port/oscillator crystal input/external

clock source input (GPIO in Internal RC mode only,

OSC1 in all other oscillator modes). TTL input when

GPIO, ST input in external RC oscillator mode.

—

Positive supply for logic and I/O pins

—

Ground reference for logic and I/O pins

Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input,

ST = Schmitt Trigger input

PIC12C5XX

DS40139D-page 12

1998 Microchip Technology Inc.

3.1

Clocking Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3 and Q4. Internally, the

program counter is incremented every Q1, and the

instruction is fetched from program memory and

latched into instruction register in Q4. It is decoded

and executed during the following Q1 through Q4. The

clocks and instruction execution ﬂow is shown in

Figure 3-2 and Example 3-1.

3.2

Instruction Flow/Pipelining

An Instruction Cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g.,

GOTO

)

then two cycles are required to complete the

instruction (Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is

latched into the Instruction Register (IR) in cycle Q1.

This instruction is then decoded and executed during

the Q2, Q3, and Q4 cycles. Data memory is read

during Q2 (operand read) and written during Q4

(destination write).

FIGURE 3-2:

CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1:

INSTRUCTION PIPELINE FLOW

OSC1

PC+1

PC+2

Fetch INST (PC)

Execute INST (PC-1)

Fetch INST (PC+1)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+1)

Internal

phase

clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

1. MOVLW 03H

Fetch 1

Execute 1

2. MOVWF GPIO

Fetch 2

Execute 2

3. CALL SUB_1

Fetch 3

Execute 3

4. BSF GPIO, BIT1

Fetch 4

Flush

Fetch SUB_1 Execute SUB_1

1998 Microchip Technology Inc.

DS40139D-page 13

PIC12C5XX

4.0

MEMORY ORGANIZATION

PIC12C5XX memory is organized into program mem-

ory and data memory. For devices with more than 512

bytes of program memory, a paging scheme is used.

Program memory pages are accessed using one STA-

TUS register bit. For the PIC12C509(A) with a data

memory register ﬁle of more than 32 registers, a bank-

ing scheme is used. Data memory banks are accessed

using the File Select Register (FSR).

4.1

Program Memory Organization

The PIC12C5XX devices have a 12-bit Program

Counter (PC) capable of addressing a 2K x 12

program memory space.

Only the ﬁrst 512 x 12 (0000h-01FFh) for the

PIC12C508(A) and 1K x 12 (0000h-03FFh) for the

PIC12C509(A) are physically implemented. Refer to

Figure 4-1. Accessing a location above these

boundaries will cause a wrap-around within the ﬁrst

512 x 12 space (PIC12C508(A)) or 1K x 12 space

(PIC12C509(A)). The effective reset vector is at 000h,

(see Figure 4-1). Location 01FFh (PIC12C508(A)) or

location 03FFh (PIC12C509(A)) contains the internal

clock oscillator calibration value. This value should

never be overwritten.

FIGURE 4-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC12C5XX

CALL, RETLW

PC<11:0>

Stack Level 1

Stack Level 2

User Memor

Space

0000h

7FFh

01FFh

0200h

On-chip Program

Memory

Reset Vector (note 1)

Note 1: Address 0000h becomes the

effective reset vector. Location