/home/techdatasheets.com/WWW/datasheets_html/328422/datasheet-GMS90C320PL50

Version 1.2

Published by

MCU Application Team

Copy right

Additional information of this manual may be served by Hynix semiconductor offices in Korea or Distributors and Repre-

sentatives listed at address directory.

Hynix semiconductor reserves the right to make changes to any information here in at any time without notice.

The information, diagrams and other data in this manual are correct and reliable; however, Hynix semiconductor is in no

way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

REVISION HISTORY

VERSION 1.2 (Oct. 2000) This book

Correct the pin number of 44-MQFP package type on page 6.

VERSION 1.1 (Oct. 1999) Before version

GMS90C320

OCT. 2000 Ver 1.2

GMS90C320/L320

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

ROM-less Version for 90C52

Features

• Fully compatible to standard MCS-51 microcontroller

• Versions for 40/50 MHz operating frequency

• Low voltage version for 24MHz operating frequency

• 256 bytes of on-chip data RAM

• 64K external program memory space

• 64K external data memory space

• Four 8-bit ports

• Three 16-bit Timers/Counters (Timer 2 with up/down counter feature)

• USART

• Six interrupt sources, two priority levels

• Power saving Idle and power down mode

• 2.7Volt low voltage version available

• P-DIP-40, P-LCC-44, P-MQFP-44 package

The GMS90C320 described in this document is compatible with the standard 80C32 can be used for all present standard

80C32 applications.

Operating Voltage (V)

Device Name

ROM

RAM

Operating

Frequency (MHz)

4.25~5.5

GMS90C320

ROM-less

256

××××

8bit

40/50

2.7~5.5

GMS90L320

ROM-less

256

××××

8bit

RAM

256 x 8

ROM-less

CPU

8-BIT

USART

PORT0

PORT3

PORT1

PORT2

I/O

GMS90C320

OCT. 2000 Ver 1.2

44-PLCC Pin Configuration

(top view)

(P-LCC-44)

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

N.C.

ALE

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

N.C.

/P3

XTA

N.C.

/A8

/A9

P1.5

P1.6

P1.7

RESET

RxD/P3.0

N.C.

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

GMS90C320

OCT. 2000 Ver 1.2

40-PDIP Pin Configuration

(top view)

(P-DIP-40)

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

ALE

PSEN

P1.6

P1.7

RESET

RxD/P3.0

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

WR/P3.6

RD/P3.7

T2/P1.0

T2EX/P1.1

P1.2

P1.3

P1.4

P1.5

XTAL2

XTAL1

S S

C C

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P2.0/A8

GMS90C320

OCT. 2000 Ver 1.2

44-PLCC Pin Configuration

(top view)

(P-MQFP-44)

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

N.C.

ALE

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

P1.5

P1.6

P1.7

RESET

RxD/P3.0

N.C.

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

GMS90C320

OCT. 2000 Ver 1.2

Pin Definitions and functions

Symbol

Pin Number

Input/

Output

Function

P-LCC-44

P-DIP-40

P-MQFP-

P1.0-P1.7

2-9

1-8

40-44,

1-3

I/O

Port1

is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins

that have 1s written to them are pulled high by the internal pull-up

resistors and can be used as inputs. As inputs, port 1 pins that are

externally pulled low will source current because of the pulls-ups

, in the DC characteristics). Pins P1.0 and P1.1 also. Port 1

also receives the low-order address byte during program memory

verification. Port1 also serves alternate functions of Timer 2.

P1.0/T2: Timer/counter 2 external count input

P1.1/T2EX: Timer/counter 2 trigger input

P3.0-P3.7

11,13-

10-17

5, 7-

I/O

Port 3

is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins

that have 1s written to them are pulled high by the internal pull-up

resistors, and in that state they can be used as inputs. As inputs,

port 3 pins being externally pulled low will source current (I

, in

the DC characteristics) because of internal pulls-up resistors. Port

3 also serves the special features of the 80C51 family, as listed

below.

P3.0/RxD

receiver data input (asynchronous) or data input

output (synchronous) of the serial interface 0

P3.1 / TxD

transmitter data output (asynchronous) or clock

output (synchronous) of the serial interface 0

P3.2 / INT0

interrupt 0 input / timer 0 gate control

P3.3 / INT1

interrupt 1 input / timer 1 gate control

P3.4 / T0

counter 0 input

P3.5 / T1

counter 1 input

P3.6 / WR

the write control signal latches the data byte from

port 0 into the external data memory

P3.7 / RD

the read control signal enables the external data

memory to port 0

XTAL2

XTAL2

Output of the inverting oscillator amplifier

XTAL1

XTAL1

Input to the inverting oscillator amplifier and input to the internal

clock generator circuits.

To drive the device from an external clock source, XTAL1 should

be driven, while XTAL2 is left unconnected. There are no require-

ments on the duty cycle of the external clock signal, since the

input to the internal clocking circuitry is divided down by a divide-

by-two flip-flop. Minimum and maximum high and low times as

well as rise fall times specified in the AC characteristics must be

observed.

GMS90C320

OCT. 2000 Ver 1.2

P2.0-P2.7

24-31

21-28

18-25

I/O

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2

pins that have 1s written to them are pulled high by the internal

pull-up resistors and can be used as inputs. As inputs, port 2 pins

that are externally pulled low will source current because of the

pulls-ups (I

, in the DC characteristics). Port 2 emits the high-

order address byte during fetches from external program memory

and during accesses to external data memory that use 16-bit

addresses (MOVX @DPTR). In this application it uses strong

internal pull-ups when emitting 1s. During accesses to external

data memory that use 8-bit addresses (MOVX @Ri), port 2 emits

the contents of the P2 special function register.

PSEN

The Program Store Enable

The read strobe to external program memory when the device is

executing code from the external program memory. PSEN is acti-

vated twice each machine cycle, except that two PSEN activation

are skipped during each access to external data memory. PSEN

is not activated during fetches from internal program memory.

RESET

RESET

A high level on this pin for two machine cycles while the oscillator

is running resets the device. An internal diffused resistor to V

S S

permits power-on reset using only an external capacitor to V

C C

ALE

The Address Latch Enable

Output pulse for latching the low byte of the address during an

access to external memory. In normal operation, ALE is emitted

at a constant rate of 1/6 the oscillator frequency, and can be used

for external timing or clocking. Note that one ALE pulse is skipped

during each access to external data memory.

External Access Enable

EA must be external held low to enable the device to fetch code

from external program memory locations 0000

to FFFF

. If EA is

held high, the device executes from internal program memory

unless the program counter contains an address greater than its

internal memory size.

P0.0-P0.7

43-36

39-32

37-30

I/O

Port 0

Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that

have 1s written to them float and can be used as high-impedance

inputs. Port 0 is also the multiplexed low-order address and data

bus during accesses to external program and data memory. In

this application it uses strong internal pull-ups when emitting 1s.

Port 0 also outputs the code bytes during program verification in

the GMS97C5x. External pull-up resistors are required during

program verification.

S S

Circuit ground potential

C C

Supply terminal for all operating modes

N.C.

1,12,

23,34

6,17,

28,39

No connection

Symbol

Pin Number

Input/

Output

Function

P-LCC-44

P-DIP-40

P-MQFP-

GMS90C320

OCT. 2000 Ver 1.2

Function Description

The GMS90 series is fully compatible to the standard 8051 microcontroller family.

It is compatible with the standard 80C32. While maintaining all architectural and operational characteristics of the standard

80C32, the GMS90C320 incorporates some enhancements in the Timer 2 unit.

Figure 1 shows a block diagram of the GMS90C320

Figure 1 Block Diagram of the GMS90C320

RAM

256 x 8

Port 0

8-bit Digital I/O

Port 1

8-bit Digital I/O

Port 2

8-bit Digital I/O

Port 3

8-bit Digital I/O

CPU

Timer 0

Timer 1

Timer 2

Interrupt Unit

Serial Channel

OSC & Timing

XTAL1

XTAL2

RESET

ALE

PSEN

GMS90C320

OCT. 2000 Ver 1.2

CPU

The GMS90C320 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD

arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set con-

sisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are

executed in 1.0

Special Function Register PSW

Reset value of PSW is 00

H .

Bit

Function

Carry Flag

Auxiliary Carry Flag (for BCD operation)

General Purpose Flag

RS1

RS0

Register Bank select control bits

Bank 0 selected, data address 00

-07

Bank 1 selected, data address 08

-0F

Bank 2 selected, data address 10

-17

Bank 3 selected, data address 18

-1F

Overflow Flag

General Purpose Flag

Parity Flag

Set/cleared by hardware each instruction cycle to indicate an odd/

even number of “one” bits in the accumulator, i.e. even parity.

MSB

LSB

Bit No.

Addr. D0

RS1

RS2

PSW

GMS90C320

OCT. 2000 Ver 1.2

Special Function Registers

All registers, except the program counter and the four general purpose register banks, reside in the special function register

area.

The 27 special function registers (SFR) include pointers and registers that provide an interface between the CPU and the other

on-chip peripherals. There are also 128 directly addressable bits within the SFR area.

All SFRs are listed in Table 1, Table 2, and Table 3.

In Table 1 they are organized in numeric order of their addresses. In Table 2 they are organized in groups which refer to the

functional blocks of the GMS90C320. Table 3 illustrates the contents of the SFRs.

Table 1

Special Function Registers in Numeric Order of their Addresses

Address

Register

Contents after

Reset

Address

Register

Contents after

Reset

DPL

DPH

reserved

PCON

: Bit-addressable Special Function Register

H 2)

0XXX0000

B2)

: X means that the value is indeterminate and the location is reserved

reserved

H 2)

TCON

TMOD

TL0

TL1

TH0

TH1

reserved

0X000000

B2)

H 2)

reserved