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NT128D64S88A2GM

128MB : 16M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

Preliminary

01/2002

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

200pin One Bank Unbuffered DDR SO-DIMM

Based on DDR266/200 16Mx8 SDRAM

Features

•

JEDEC Standard 200-Pin Small Outline Dual In-Line Memory

Module (SO-DIMM)

• 16Mx64 Double Unbuffered DDR SO-DIMM based on 16Mx8

DDR SDRAM.

• Performance :

PC1600

PC2100

Speed Sort

- 8B

- 75B

- 7K

DIMM CAS Latency

2.5

Unit

Clock Frequency

100

133

MHz

Clock Cycle

7.5

DQ Burst Frequency

200

266

MHz

• Intended for 100 MHz and 133 MHz applications

• Inputs and outputs are SSTL-2 compatible

• V

= 2.5Volt ±

0.2, V

DDQ

= 2.5Volt ± 0.2

• Single Pulsed RAS interface

• SDRAMs have 4 internal banks for concurrent operation

• Module has one physical bank

• Differential clock inputs

• Data is read or written on both clock edges

• DRAM D

aligns DQ and DQS transitions with clock

transitions.

• Address and control signals are fully synchronous to positive

clock edge

• Programmable Operation:

- DIMM CAS Latency: 2, 2.5

- Burst Type: Sequential or Interleave

- Burst Length: 2, 4, 8

- Operation: Burst Read and Write

• Auto Refresh (CBR) and Self Refresh Modes

• Automatic and controlled precharge commands

• 12/10/2 Addressing (row/column/bank)

• 15.6

s Max. Average Periodic Refresh Interval

• Serial Presence Detect

• Gold contacts

• SDRAMs in 66-pin TSOP Type II Package

Description

NT128D64S88A2GM is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),

organized as a one-bank high-speed memory array. The 16Mx64 module is a single-bank DIMM that uses eight 16Mx8 DDR

SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use

in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all

devices on the DIMM.

Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by

address inputs A0-A11 and I/O inputs BA0 and BA1 using the mode register set cycle.

These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common

design files minimizes electrical variation between suppliers.

The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD

data are programmed and locked during module assembly. The last 128 bytes are available to the customer.

All NANYA 200 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a2.66” long space-saving footprint.

Ordering Information

Part Number

Speed

Organization

Leads

Power

143MHz (7ns @ CL = 2.5 )

NT128D64S88A2GM-7K

133MHz (7.5ns @ CL= 2 )

PC2100

133MHz (7.5ns @ CL= 2.5 )

NT128D64S88A2GM –75B

100MHz (10ns @ CL = 2 )

PC2100

125MHz (8ns @ CL = 2.5 )

NT128D64S88A2GM –8B

100MHz (10ns @ CL = 2 )

PC1600

16Mx64

Gold

2.5V

NT128D64S88A2GM

128MB : 16M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

Preliminary

01/2002

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Description

CK0, CK1, CK2

CK0 , CK1 , CK2

Differential Clock Inputs

DQ0-DQ63

Data input/output

CKE0

Clock Enable

DQS0-DQS7

Bidirectional data strobes

RAS

Row Address Strobe

DM0-DM7

Data Masks

CAS

Column Address Strobe

VDD

Power (2.5V)

Write Enable

DDQ

Supply voltage for DQs(2.5V)

Chip Selects

Ground

A0-A9, A11

Address Inputs

No Connect

A10/AP

Address Input/Autoprecharge

SCL

Serial Presence Detect Clock Input

BA0, BA1

SDRAM Bank Address Inputs

SDA

Serial Presence Detect Data input/output

REF

Ref. Voltage for SSTL_2 inputs

SA0-2

Serial Presence Detect Address Inputs

DDID

Identification flag.

(Not used when V

DDQ)

DDSPD

Serial EEPROM positive power supply(2.5V)

Pinout

Front

Back

Front

Back

Front

Back

Front

Back

REF

101

102

151

DQ42

152

DQ46

DQ19

DQ23

103

104

153

DQ43

154

DQ47

DQ0

DQ4

DQ24

DQ28

105

106

155

156

DQ1

DQ5

107

108

157

158

CK1

DQ25

DQ29

109

110

159

160

CK1

DQS0

DM0

DQS3

DM3

111

112

161

162

DQ2

DQ6

113

114

163

DQ48

164

DQ52

DQ26

DQ30

115

A10/AP

116

BA1

165

DQ49

166

DQ53

DQ3

DQ7

DQ27

DQ31

117

118

RAS 167

168

DQ8

DQ12

119

120

CAS 169

DQS6

170

DM6

121

122

171

DQ50

172

DQ54

DQ9

DQ13

123

124

173

174

DQS1

DM1

125

126

175

DQ51

176

DQ55

127

DQ32

128

DQ36 177

DQ56

178

DQ60

DQ10

DQ14

129

DQ33

130

DQ37 179

180

DQ11

DQ15

131

132

181

DQ57

182

DQ61

133

DQS4

134

DM4

183

DQS7

184

DM7

CK0

135

DQ34

136

DQ38 185

186

CK0

137

138

187

DQ58

188

DQ62

139

DQ35

140

DQ39 189

DQ59

190

DQ63

DQ16

DQ20

141

DQ40

142

DQ44 191

192

DQ17

DQ21

143

144

193

SDA

194

SA0

CKE1

CKE0

145

DQ41

146

DQ45 195

SCL

196

SA1

DQS2

DM2

147

DQS5

148

DM5

197 V

DDSPD

198

SA2

DQ18

DQ22

100

A11

149

150

199

DDID

200

Note: All pin assignments are consistent for all 8-byte unbuffered versions.

NT128D64S88A2GM

128MB : 16M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

Preliminary

01/2002

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Input/Output Functional Description

Symbol

Type

Polarity

Function

CK0 , CK1, CK2

(SSTL)

Positive

Edge

The positive line of the differential pair of system clock inputs which drives the input to the

on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the rising

edge of their associated clocks.

CK0 , CK1 , CK2

(SSTL)

Negative

Edge

The negative line of the differential pair of system clock inputs which drives the input to the

on-DIMM PLL.

CKE0

(SSTL)

Active

High

Activates the SDRAM CK signal when high and deactivates the CK signal when low. By

deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh

mode.

(SSTL)

Active

Low

Enables the associated SDRAM command decoder when low and disables the command

decoder when high. When the command decoder is disabled, new commands are ignored

but previous operations continue.

RAS

CAS

(SSTL)

Active

Low

When sampled at the positive rising edge of the clock, RAS

CAS

WE define the

operation to be executed by the SDRAM.

REF

Supply

Reference voltage for SSTL-2 inputs

DDQ

Supply

Isolated power supply for the DDR SDRAM output buffers to provide improved noise

immunity

BA0, BA1

(SSTL)

Selects which SDRAM bank is to be active.

A0 - A9

A10/AP

A11

(SSTL)

During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)

when sampled at the rising clock edge.

During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)

when sampled at the rising clock edge. In addition to the column address, AP is used to

invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,

autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,

autoprecharge is disabled.

During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control

which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the

state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.

DQ0 - DQ63,

(SSTL)

Data and Check Bit input/output pins operate in the same manner as on conventional

DRAMs.

DQS0 - DQS7

(SSTL)

Active

High

Data strobes: Output with read data, input with write data. Edge aligned with read data,

centered on write data. Used to capture write data.

DM0 – DM7

Input

Active

High

The data write masks, associated with one data byte. In Write mode, DM operates as a

byte mask by allowing input data to be written if it is low but blocks the write operation if it

is high. In Read mode, DM lines have no effect. DM8 is associated with check bits

CB0-CB7, and is not used on x64 modules.

, V

Supply

Power and ground for the DDR SDRAM input buffers and core logic

SA0 – SA2

Address inputs. Connected to either VDD or VSS on the system board to configure the

Serial Presence Detect EEPROM address.

SDA

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor

must be connected from the SDA bus line to V

to act as a pullup.

SCL

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from the SCL bus time to V

to act as a pullup.

DDSPD

Supply

Serial EEPROM positive power supply.

NT128D64S88A2GM

128MB : 16M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

Preliminary

01/2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Functional Block Diagram

( 1 Bank, 16Mx8 DDR SDRAMs )

DM0

DQ0

DQ1

DQ2

DQ7

DQ4

DQ6

DQ5

DQ3

DQ8

DQ9

DQ10

DQ15

DQ12

DQ14

DQ13

DQ11

A0-A12

RAS

BA0-BA1

CS : SDRAMs D0 -D7

BA0 - BA1 : SDRAMs D0 -D7

A0 - A12: SDRAMs D0 -D7

RAS : SDRAMs D0 -D7

DQ16

DQ17

DQ18

DQ23

DQ20

DQ22

DQ21

DQ19

DQ24

DQ25

DQ26

DQ31

DQ28

DQ30

DQ29

DQ27

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

VDDQ

VSS

D0 - D7

Serial PD

SCL

SDA

SA0

SA2

SA1

DQS0

DM4

DQS4

DQS

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQS

DM1

DQS1

DQS

DM2

DQS2

DM3

DQS3

DQS

DQ32

DQ33

DQ34

DQ39

DQ36

DQ38

DQ37

DQ35

DQ40

DQ41

DQ42

DQ47

DQ44

DQ46

DQ45

DQ43

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQS

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQS

DQS5

DM5

DQ48

DQ49

DQ50

DQ55

DQ52

DQ54

DQ53

DQ51

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQS

DQ56

DQ57

DQ58

DQ63

DQ60

DQ62

DQ61

DQ59

I/O 0

I/O 1

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

DQS

DQS6

DM6

DQS7

DM7

CKE0

CAS

CAS : SDRAMs D0 -D7

CKE0 : SDRAMs D0 -D7

WE : SDRAMs D0 -D7

120 ohm

SDRAM x 4

CK0

120 ohm

SDRAM x 4

CK1

120 ohm

SDRAM x 0

CK2

D0 - D7

VDD

VREF

VDDID

Notes :

1. DQ-to-I/O wring may be changed within a byte.

2. DQ/DQS/DM/CKE/S relationships are maintained as shown.

3. DQ/DQS/DM/DQS resistors are 22 Ohms.

4. VDDID strap connections (for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

STRAP IN (VSS): VDD is not equal to VDDQ.

Strap: see Note 4