Xilinx XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) datasheet, v3.1 (11/98)

November 9, 1998 (Version 3.1)

7-3

Features

•

Complete line of four related Field Programmable Gate

Array product families

XC3000A, XC3000L, XC3100A, XC3100L

•

Ideal for a wide range of custom VLSI design tasks

Replaces TTL, MSI, and other PLD logic

Integrates complete sub-systems into a single

package

Avoids the NRE, time delay, and risk of conventional

masked gate arrays

•

High-performance CMOS static memory technology

Guaranteed toggle rates of 70 to 370 MHz, logic

delays from 7 to 1.5 ns

System clock speeds over 85 MHz

Low quiescent and active power consumption

•

Flexible FPGA architecture

Compatible arrays ranging from 1,000 to 7,500 gate

complexity

Extensive register, combinatorial, and I/O

capabilities

High fan-out signal distribution, low-skew clock nets

Internal 3-state bus capabilities

TTL or CMOS input thresholds

On-chip crystal oscillator amplifier

•

Unlimited reprogrammability

Easy design iteration

In-system logic changes

•

Extensive packaging options

Over 20 different packages

Plastic and ceramic surface-mount and pin-grid-

array packages

Thin and Very Thin Quad Flat Pack (TQFP and

VQFP) options

•

Ready for volume production

Standard, off-the-shelf product availability

100% factory pre-tested devices

Excellent reliability record

•

Complete Development System

Schematic capture, automatic place and route

Logic and timing simulation

Interactive design editor for design optimization

Timing calculator

Interfaces to popular design environments like

Viewlogic, Cadence, Mentor Graphics, and others

Additional XC3100A Features

•

Ultra-high-speed FPGA family with six members

50-85 MHz system clock rates

190 to 370 MHz guaranteed flip-flop toggle rates

1.55 to 4.1 ns logic delays

•

High-end additional family member in the 22 X 22 CLB

array-size XC3195A device

•

8 mA output sink current and 8 mA source current

•

Maximum power-down and quiescent current is 5 mA

•

100% architecture and pin-out compatible with other

XC3000 families

•

Software and bitstream compatible with the XC3000,

XC3000A, and XC3000L families

XC3100A combines the features of the XC3000A and

XC3100 families:

•

Additional interconnect resources for TBUFs and CE

inputs

•

Error checking of the configuration bitstream

•

Soft startup holds all outputs slew-rate limited during

initial power-up

•

More advanced CMOS process

Low-Voltage Versions Available

•

Low-voltage devices function at 3.0 - 3.6 V

•

XC3000L - Low-voltage versions of XC3000A devices

•

XC3100L - Low-voltage versions of XC3100A devices

XC3000 Series

Field Programmable Gate Arrays

(XC3000A/L, XC3100A/L)

November 9, 1998 (Version 3.1)

Product Description

Device

Max Logic

Gates

Typical Gate

Range

CLBs

Array

User I/Os

Max

Flip-Flops

Horizontal

Longlines

Configuration

Data Bits

XC3020A, 3020L, 3120A

1,500

1,000 - 1,500

8 x 8

256

14,779

XC3030A, 3030L, 3130A

2,000

1,500 - 2,000

100

10 x 10

360

22,176

XC3042A, 3042L, 3142A, 3142L

3,000

2,000 - 3,000

144

12 x 12

480

30,784

XC3064A, 3064L, 3164A

4,500

3,500 - 4,500

224

16 x 14

120

688

46,064

XC3090A, 3090L, 3190A, 3190L

6,000

5,000 - 6,000

320

16 x 20

144

928

64,160

XC3195A

7,500

6,500 - 7,500

484

22 x 22

176

1,320

94,984

XC3000 Series Field Programmable Gate Arrays

7-4

November 9, 1998 (Version 3.1)

Introduction

XC3000-Series Field Programmable Gate Arrays (FPGAs)

provide a group of high-performance, high-density, digital

integrated circuits. Their regular, extendable, flexible,

user-programmable array architecture is composed of a

configuration program store plus three types of config-

urable elements: a perimeter of I/O Blocks (IOBs), a core

array of Configurable Logic Bocks (CLBs) and resources

for interconnection. The general structure of an FPGA is

shown in

Figure 2

. The development system provides

schematic capture and auto place-and-route for design

entry. Logic and timing simulation, and in-circuit emulation

are available as design verification alternatives. The design

editor is used for interactive design optimization, and to

compile the data pattern that represents the configuration

program.

The FPGA user logic functions and interconnections are

determined by the configuration program data stored in

internal static memory cells. The program can be loaded in

any of several modes to accommodate various system

requirements. The program data resides externally in an

EEPROM, EPROM or ROM on the application circuit

board, or on a floppy disk or hard disk. On-chip initialization

logic provides for optional automatic loading of program

data at power-up. The companion XC17XX Serial Configu-

ration PROMs provide a very simple serial configuration

program storage in a one-time programmable package.

The XC3000 Field Programmable Gate Array families pro-

vide a variety of logic capacities, package styles, tempera-

ture ranges and speed grades.

XC3000 Series Overview

There are now four distinct family groupings within the

XC3000 Series of FPGA devices:

•

XC3000A Family

•

XC3000L Family

•

XC3100A Family

•

XC3100L Family

All four families share a common architecture, develop-

ment software, design and programming methodology, and

also common package pin-outs. An extensive Product

Description covers these common aspects.

Detailed parametric information for the XC3000A,

XC3000L, XC3100A, and XC3100L product families is then

provided. (The XC3000 and XC3100 families are not rec-

ommended for new designs.)

Here is a simple overview of those XC3000 products cur-

rently emphasized:

•

XC3000A Family — The XC3000A is an enhanced

version of the basic XC3000 family, featuring additional

interconnect resources and other user-friendly

enhancements.

•

XC3000L Family — The XC3000L is identical in

architecture and features to the XC3000A family, but

operates at a nominal supply voltage of 3.3 V. The

XC3000L is the right solution for battery-operated and

low-power applications.

•

XC3100A Family — The XC3100A is a

performance-optimized relative of the XC3000A family.

While both families are bitstream and footprint

compatible, the XC3100A family extends toggle rates to

370 MHz and in-system performance to over 80 MHz.

The XC3100A family also offers one additional array

size, the XC3195A.

•

XC3100L Family — The XC3100L is identical in

architectures and features to the XC3100A family, but

operates at a nominal supply voltage of 3.3V.

Figure 1

illustrates the relationships between the families.

Compared to the original XC3000 family, XC3000A offers

additional functionality and increased speed. The XC3000L

family offers the same additional functionality, but reduced

speed due to its lower supply voltage of 3.3 V. The

XC3100A family offers substantially higher speed and

higher density with the XC3195A.

New XC3000 Series Compared to Original

XC3000 Family

For readers already familiar with the original XC3000 family

of FPGAs, the major new features in the XC3000A,

XC3000L, XC3100A, and XC3100L families are listed in

this section.

All of these new families are upward-compatible extensions

of the original XC3000 FPGA architecture. Any bitstream

used to configure an XC3000 device will configure the cor-

responding XC3000A, XC3000L, XC3100A, or XC3100L

device exactly the same way.

The XC3100A and XC3100L FPGA architectures are

upward-compatible extensions of the XC3000A and

XC3000L architectures. Any bitstream used to configure an

XC3000A or XC3000L device will configure the corre-

sponding XC3100A or XC3100L device exactly the same

way.

November 9, 1998 (Version 3.1)

7-5

XC3000 Series Field Programmable Gate Arrays

Improvements in the XC3000A and XC3000L

Families

The XC3000A and XC3000L families offer the following

enhancements over the popular XC3000 family:

The XC3000A and XC3000L families have additional inter-

connect resources to drive the I-inputs of TBUFs driving

horizontal Longlines. The CLB Clock Enable input can be

driven from a second vertical Longline. These two additions

result in more efficient and faster designs when horizontal

Longlines are used for data bussing.

During configuration, the XC3000A and XC3000L devices

check the bit-stream format for stop bits in the appropriate

positions. Any error terminates the configuration and pulls

INIT Low.

When the configuration process is finished and the device

starts up in user mode, the first activation of the outputs is

automatically slew-rate limited. This feature, called Soft

Startup, avoids the potential ground bounce when all

out-puts are turned on simultaneously. After start-up, the

slew rate of the individual outputs is, as in the XC3000 fam-

ily, determined by the individual configuration option.

Improvements in the XC3100A and XC3100L

Families

Based on a more advanced CMOS process, the XC3100A

and XC3100L families are architecturally-identical, perfor-

mance-optimized relatives of the XC3000A and XC3000L

families. While all families are footprint compatible, the

XC3100A family extends achievable system performance

beyond 85 MHz.

XC3100

XC3100A

(XC3195A)

Gate Capacity

X7068

Functionality

XC3000L

XC3000A

XC3100L

Speed

Figure 1: XC3000 FPGA Families

XC3000 Series Field Programmable Gate Arrays

7-6

November 9, 1998 (Version 3.1)

Detailed Functional Description

The perimeter of configurable Input/Output Blocks (IOBs)

provides a programmable interface between the internal

logic array and the device package pins. The array of Con-

figurable Logic Blocks (CLBs) performs user-specified logic

functions. The interconnect resources are programmed to

form networks, carrying logic signals among blocks, analo-

gous to printed circuit board traces connecting MSI/SSI

packages.

The block logic functions are implemented by programmed

look-up tables. Functional options are implemented by pro-

gram-controlled multiplexers. Interconnecting networks

between blocks are implemented with metal segments

joined by program-controlled pass transistors.

These FPGA functions are established by a configuration

program which is loaded into an internal, distributed array

of configuration memory cells. The configuration program

is loaded into the device at power-up and may be reloaded

on command. The FPGA includes logic and control signals

to implement automatic or passive configuration. Program

data may be either bit serial or byte parallel. The develop-

ment system generates the configuration program bit-

stream used to configure the device. The memory loading

process is independent of the user logic functions.

Configuration Memory

The static memory cell used for the configuration memory

in the Field Programmable Gate Array has been designed

specifically for high reliability and noise immunity. Integrity

of the device configuration memory based on this design is

assured even under adverse conditions. As shown in

Figure 3

, the basic memory cell consists of two CMOS

inverters plus a pass transistor used for writing and reading

cell data. The cell is only written during configuration and

only read during readback. During normal operation, the

cell provides continuous control and the pass transistor is

off and does not affect cell stability. This is quite different

from the operation of conventional memory devices, in

which the cells are frequently read and rewritten.

GND

PWR

P11

P12

P13

U61

TCL

KIN

3-State Buffers With Access

to Horizontal Long Lines

Configurable Logic

Blocks

Interconnect Area

Frame Pointer

Configuration Memory

I/O Blocks

X3241

Figure 2: Field Programmable Gate Array Structure.

It consists of a perimeter of programmable I/O blocks, a core of configurable logic blocks and their interconnect resources.

These are all controlled by the distributed array of configuration program memory cells.

November 9, 1998 (Version 3.1)

7-7

XC3000 Series Field Programmable Gate Arrays

The memory cell outputs Q and Q use ground and V

lev-

els and provide continuous, direct control. The additional

capacitive load together with the absence of address

decoding and sense amplifiers provide high stability to the

cell. Due to the structure of the configuration memory cells,

they are not affected by extreme power-supply excursions

or very high levels of alpha particle radiation. In reliability

testing, no soft errors have been observed even in the

presence of very high doses of alpha radiation.

The method of loading the configuration data is selectable.

Two methods use serial data, while three use byte-wide

data. The internal configuration logic utilizes framing infor-

mation, embedded in the program data by the development

system, to direct memory-cell loading. The serial-data

framing and length-count preamble provide programming

compatibility for mixes of various FPGA device devices in a

synchronous, serial, daisy-chain fashion.

I/O Block

Each user-configurable IOB shown in

Figure 4

, provides an

interface between the external package pin of the device

and the internal user logic. Each IOB includes both regis-

tered and direct input paths. Each IOB provides a program-

mable 3-state output buffer, which may be driven by a

registered or direct output signal. Configuration options

allow each IOB an inversion, a controlled slew rate and a

high impedance pull-up. Each input circuit also provides

input clamping diodes to provide electrostatic protection,

and circuits to inhibit latch-up produced by input currents.

Data

Read or

Write

Configuration

Control

X5382

Figure 3: Static Configuration Memory Cell.

It is loaded with one bit of configuration program and con-

trols one program selection in the Field Programmable

Gate Array.

FLIP

FLOP

SLEW

RATE

PASSIVE

PULL UP

OUTPUT

SELECT

3-STATE

INVERT

OUT

INVERT

FLIP

FLOP

LATCH

REGISTERED IN

DIRECT IN

OUT

3- STATE

(OUTPUT ENABLE)

TTL or

CMOS

INPUT

THRESHOLD

OUTPUT

BUFFER

(GLOBAL RESET)

CK1

X3029

I/O PAD

Vcc

PROGRAM-CONTROLLED MEMORY CELLS

PROGRAMMABLE INTERCONNECTION POINT or PIP

PROGRAM

CONTROLLED

MULTIPLEXER

CK2

Figure 4: Input/Output Block.

Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice

of two clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable.

A clock line that triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice

versa. Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS

thresholds.

XC3000 Series Field Programmable Gate Arrays

7-8

November 9, 1998 (Version 3.1)

The input-buffer portion of each IOB provides threshold

detection to translate external signals applied to the pack-

age pin to internal logic levels. The global input-buffer

threshold of the IOBs can be programmed to be compatible

with either TTL or CMOS levels. The buffered input signal

drives the data input of a storage element, which may be

configured as either a flip-flop or a latch. The clocking

polarity (rising/falling edge-triggered flip-flop, High/Low

transparent latch) is programmable for each of the two

clock lines on each of the four die edges. Note that a clock

line driving a

rising edge-triggered flip-flop makes any latch

driven by the same line on the same edge Low-level trans-

parent and vice versa (

falling edge, High transparent). All

Xilinx primitives in the supported schematic-entry pack-

ages, however, are positive edge-triggered flip-flops or

High transparent latches. When one clock line must drive

flip-flops as well as latches, it is necessary to compensate

for the difference in clocking polarities with an additional

inverter either in the flip-flop clock input or the latch-enable

input. I/O storage elements are reset during configuration

or by the active-Low chip RESET input. Both direct input

(from IOB pin I) and registered input (from IOB pin Q) sig-

nals are available for interconnect.

For reliable operation, inputs should have transition times

of less than 100 ns and should not be left floating. Floating

CMOS input-pin circuits might be at threshold and produce

oscillations. This can produce additional power dissipation

and system noise. A typical hysteresis of about 300 mV

reduces sensitivity to input noise. Each user IOB includes a

programmable high-impedance pull-up resistor, which may

be selected by the program to provide a constant High for

otherwise undriven package pins. Although the Field Pro-

grammable Gate Array provides circuitry to provide input

protection for electrostatic discharge, normal CMOS han-

dling precautions should be observed.

Flip-flop loop delays for the IOB and logic-block flip-flops

are short, providing good performance under asynchro-

nous clock and data conditions. Short loop delays minimize

the probability of a metastable condition that can result

from assertion of the clock during data transitions. Because

of the short-loop-delay characteristic in the Field Program-

mable Gate Array, the IOB flip-flops can be used to syn-

chronize external signals applied to the device. Once

synchronized in the IOB, the signals can be used internally

without further consideration of their clock relative timing,

except as it applies to the internal logic and routing-path

delays.

IOB output buffers provide CMOS-compatible 4-mA

source-or-sink drive for high fan-out CMOS or TTL- com-

patible signal levels (8 mA in the XC3100A family). The net-

work driving IOB pin O becomes the registered or direct

data source for the output buffer. The 3-state control signal

(IOB) pin T can control output activity. An open-drain output

may be obtained by using the same signal for driving the

output and 3-state signal nets so that the buffer output is

enabled only for a Low.

Configuration program bits for each IOB control features

such as optional output register, logic signal inversion, and

3-state and slew-rate control of the output.

The program-controlled memory cells of

Figure 4

control

the following options.

•

Logic inversion of the output is controlled by one

configuration program bit per IOB.

•

Logic 3-state control of each IOB output buffer is

determined by the states of configuration program bits

that turn the buffer on, or off, or select the output buffer

3-state control interconnection (IOB pin T). When this

IOB output control signal is High, a logic one, the buffer

is disabled and the package pin is high impedance.

When this IOB output control signal is Low, a logic zero,

the buffer is enabled and the package pin is active.

Inversion of the buffer 3-state control-logic sense

(output enable) is controlled by an additional

configuration program bit.

•

Direct or registered output is selectable for each IOB.

The register uses a positive-edge, clocked flip-flop. The

clock source may be supplied (IOB pin OK) by either of

two metal lines available along each die edge. Each of

these lines is driven by an invertible buffer.

•

Increased output transition speed can be selected to

improve critical timing. Slower transitions reduce

capacitive-load peak currents of non-critical outputs

and minimize system noise.

•

An internal high-impedance pull-up resistor (active by

default) prevents unconnected inputs from floating.

Unlike the original XC3000 series, the XC3000A,

XC3000L, XC3100A, and XC3100L families include the

Soft Startup feature. When the configuration process is fin-

ished and the device starts up in user mode, the first activa-

tion of the outputs is automatically slew-rate limited. This

feature avoids potential ground bounce when all outputs

are turned on simultaneously. After start-up, the slew rate

of the individual outputs is determined by the individual

configuration option.

Summary of I/O Options

•

Inputs

Direct

Flip-flop/latch

CMOS/TTL threshold (chip inputs)

Pull-up resistor/open circuit

•

Outputs

Direct/registered

Inverted/not

3-state/on/off

Full speed/slew limited

3-state/output enable (inverse)

November 9, 1998 (Version 3.1)

7-9

XC3000 Series Field Programmable Gate Arrays

Configurable Logic Block

The array of CLBs provides the functional elements from

which the user’s logic is constructed. The logic blocks are

arranged in a matrix within the perimeter of IOBs. For

example, the XC3020A has 64 such blocks arranged in 8

rows and 8 columns. The development system is used to

compile the configuration data which is to be loaded into

the internal configuration memory to define the operation

and interconnection of each block. User definition of CLBs

and their interconnecting networks may be done by auto-

matic translation from a schematic-capture logic diagram or

optionally by installing library or user macros.

Each CLB has a combinatorial logic section, two flip-flops,

and an internal control section. See

Figure 5

. There are:

five logic inputs (A, B, C, D and E); a common clock input

(K); an asynchronous direct RESET input (RD); and an

enable clock (EC). All may be driven from the interconnect

resources adjacent to the blocks. Each CLB also has two

outputs (X and Y) which may drive interconnect networks.

Data input for either flip-flop within a CLB is supplied from

the function F or G outputs of the combinatorial logic, or the

block input, DI. Both flip-flops in each CLB share the asyn-

chronous RD which, when enabled and High, is dominant

over clocked inputs. All flip-flops are reset by the

active-Low chip input, RESET, or during the configuration

process. The flip-flops share the enable clock (EC) which,

when Low, recirculates the flip-flops’ present states and

inhibits response to the data-in or combinatorial function

inputs on a CLB. The user may enable these control inputs

and select their sources. The user may also select the

clock net input (K), as well as its active sense within each

CLB. This programmable inversion eliminates the need to

route both phases of a clock signal throughout the device.

COMBINATORIAL

FUNCTION

LOGIC

VARIABLES

DIN

ENABLE CLOCK

CLOCK

DIRECT

RESET

1 (ENABLE)

X3032

0 (INHIBIT)

(GLOBAL RESET)

CLB OUTPUTS

DATA IN

MUX

Figure 5: Configurable Logic Block.

Each CLB includes a combinatorial logic section, two flip-flops and a program memory controlled multiplexer selection of

function. It has the following:

five logic variable inputs A, B, C, D, and E

a direct data in DI

an enable clock EC

a clock (invertible) K

an asynchronous direct RESET RD

two outputs X and Y

XC3000 Series Field Programmable Gate Arrays

7-10

November 9, 1998 (Version 3.1)

Flexible routing allows use of common or individual CLB

clocking.

The combinatorial-logic portion of the CLB uses a 32 by 1

look-up table to implement Boolean functions. Variables

selected from the five logic inputs and two internal block

flip-flops are used as table address inputs. The combinato-

rial propagation delay through the network is independent

of the logic function generated and is spike free for single

input variable changes. This technique can generate two

independent logic functions of up to four variables each as

shown in Figure 6a, or a single function of five variables as

shown in Figure 6b, or some functions of seven variables

as shown in Figure 6c.

Figure 7

shows a modulo-8 binary

counter with parallel enable. It uses one CLB of each type.

The partial functions of six or seven variables are imple-

mented using the input variable (E) to dynamically select

between two functions of four different variables. For the

two functions of four variables each, the independent

results (F and G) may be used as data inputs to either

flip-flop or either logic block output. For the single function

of five variables and merged functions of six or seven vari-

ables, the F and G outputs are identical. Symmetry of the F

and G functions and the flip-flops allows the interchange of

CLB outputs to optimize routing efficiencies of the networks

interconnecting the CLBs and IOBs.

Programmable Interconnect

Programmable-interconnection resources in the Field Pro-

grammable Gate Array provide routing paths to connect

inputs and outputs of the IOBs and CLBs into logic net-

works. Interconnections between blocks are composed of a

two-layer grid of metal segments. Specially designed pass

transistors, each controlled by a configuration bit, form pro-

grammable interconnect points (PIPs) and switching matri-

ces used to implement the necessary connections between

selected metal segments and block pins.

Figure 8

is an

example of a routed net. The development system provides

automatic routing of these interconnections. Interactive

routing is also available for design optimization. The inputs

of the CLBs or IOBs are multiplexers which can be pro-

grammed to select an input network from the adjacent

interconnect segments.

Since the switch connections to

block inputs are unidirectional, as are block outputs,

they are usable only for block input connection and not

for routing.

Figure 9

illustrates routing access to logic

block input variables, control inputs and block outputs.

Three types of metal resources are provided to accommo-

date various network interconnect requirements.

•

General Purpose Interconnect

•

Direct Connection

•

Longlines (multiplexed busses and wide AND gates)

Any Function

of Up to 4

Variables

Any Function

of Up to 4

Variables

Any Function

of 5 Variables

Any Function

of Up to 4

Variables

Any Function

of Up to 4

Variables

X5442

FGM

Mode

Figure 6: Combinational Logic Options

6a. Combinatorial Logic Option FG generates two func-

tions of four variables each. One variable, A, must be

common to both functions. The second and third variable

can be any choice of B, C, QX and QY. The fourth vari-

able can be any choice of D or E.

6b. Combinatorial Logic Option F generates any function

of five variables: A, D, E and two choices out of B, C, QX,

QY.

6c. Combinatorial Logic Option FGM allows variable E to

select between two functions of four variables: Both have

common inputs A and D and any choice out of B, C, QX

and QY for the remaining two variables. Option 3 can

then implement some functions of six or seven variables.

November 9, 1998 (Version 3.1)

7-11

XC3000 Series Field Programmable Gate Arrays

General Purpose Interconnect

General purpose interconnect, as shown in

Figure 10

, con-

sists of a grid of five horizontal and five vertical metal seg-

ments located between the rows and columns of logic and

IOBs. Each segment is the height or width of a logic block.

Switching matrices join the ends of these segments and

allow programmed interconnections between the metal grid

segments of adjoining rows and columns. The switches of

an unprogrammed device are all non-conducting. The con-

nections through the switch matrix may be established by

the automatic routing or by selecting the desired pairs of

matrix pins to be connected or disconnected. The legiti-

mate switching matrix combinations for each pin are indi-

cated in

Figure 11

Special buffers within the general interconnect areas pro-

vide periodic signal isolation and restoration for improved

performance of lengthy nets. The interconnect buffers are

available to propagate signals in either direction on a given

general interconnect segment. These bidirectional (bidi)

buffers are found adjacent to the switching matrices, above

and to the right. The other PIPs adjacent to the matrices

are accessed to or from Longlines. The development sys-

tem automatically defines the buffer direction based on the

location of the interconnection network source. The delay

calculator of the development system automatically calcu-

lates and displays the block, interconnect and buffer delays

for any paths selected. Generation of the simulation netlist

with a worst-case delay model is provided.

Direct Interconnect

Direct interconnect, shown in

Figure 12

, provides the most

efficient implementation of networks between adjacent

CLBs or I/O Blocks. Signals routed from block to block

using the direct interconnect exhibit minimum interconnect

propagation and use no general interconnect resources.

For each CLB, the X output may be connected directly to

the B input of the CLB immediately to its right and to the C

input of the CLB to its left. The Y output can use direct inter-

connect to drive the D input of the block immediately above

and the A input of the block below. Direct interconnect

should be used to maximize the speed of high-performance

portions of logic. Where logic blocks are adjacent to IOBs,

direct connect is provided alternately to the IOB inputs (I)

and outputs (O) on all four edges of the die. The right edge

provides additional direct connects from CLB outputs to

adjacent IOBs. Direct interconnections of IOBs with CLBs

are shown in

Figure 13

Count Enable

Parallel Enable

Clock

Dual Function of 4 Variables

Function of 6 Variables

Function of 5 Variables

Mode

FGM

Mode

Terminal

Count

X5383

Figure 7: Counter.

The modulo-8 binary counter with parallel enable and

clock enable uses one combinatorial logic block of each

option.

Figure 8: A Design Editor view of routing resources

used to form a typical interconnection network from

CLB GA.