May 14, 1999 (Version 1.6)
6-5
6
XC4000E and XC4000X Series
Features
Note: Information in this data sheet covers the XC4000E,
XC4000EX, and XC4000XL families. A separate data sheet
covers the XC4000XLA and XC4000XV families. Electrical
Specifications and package/pin information are covered in
separate sections for each family to make the information
easier to access, review, and print. For access to these sec-
tions, see the Xilinx W
EB
LINX web site at
.
•
System featured Field-Programmable Gate Arrays
-
Select-RAM
TM
memory: on-chip ultra-fast RAM with
-
synchronous write option
-
dual-port RAM option
-
Fully PCI compliant (speed grades -2 and faster)
-
Abundant flip-flops
-
Flexible function generators
-
Dedicated high-speed carry logic
-
Wide edge decoders on each edge
-
Hierarchy of interconnect lines
-
Internal 3-state bus capability
-
Eight global low-skew clock or signal distribution
networks
•
System Performance beyond 80 MHz
•
Flexible Array Architecture
•
Low Power Segmented Routing Architecture
•
Systems-Oriented Features
-
IEEE 1149.1-compatible boundary scan logic
support
-
Individually programmable output slew rate
-
Programmable input pull-up or pull-down resistors
-
12 mA sink current per XC4000E output
•
Configured by Loading Binary File
-
Unlimited re-programmability
•
Read Back Capability
-
Program verification
-
Internal node observability
•
Backward Compatible with XC4000 Devices
•
Development System runs on most common computer
platforms
-
Interfaces to popular design environments
-
Fully automatic mapping, placement and routing
-
Interactive design editor for design optimization
Low-Voltage Versions Available
•
Low-Voltage Devices Function at 3.0 - 3.6 Volts
•
XC4000XL: High Performance Low-Voltage Versions of
XC4000EX devices
Additional XC4000X Series Features
•
Highest Performance — 3.3 V XC4000XL
•
Highest Capacity — Over 180,000 Usable Gates
•
5 V tolerant I/Os on XC4000XL
•
0.35
µ
m SRAM process for XC4000XL
•
Additional Routing Over XC4000E
-
almost twice the routing capacity for high-density
designs
•
Buffered Interconnect for Maximum Speed Blocks
•
Improved VersaRing
TM
I/O Interconnect for Better Fixed
Pinout Flexibility
•
12 mA Sink Current Per XC4000X Output
•
Flexible New High-Speed Clock Network
-
Eight additional Early Buffers for shorter clock delays
-
Virtually unlimited number of clock signals
•
Optional Multiplexer or 2-input Function Generator on
Device Outputs
•
Four Additional Address Bits in Master Parallel
Configuration Mode
•
XC4000XV Family offers the highest density with
0.25
µ
m 2.5 V technology
Introduction
XC4000 Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased
speed, abundant routing resources, and new, sophisticated
software to achieve fully automated implementation of
complex, high-density, high-performance designs.
The XC4000E and XC4000X Series currently have 20
members, as shown in
0
XC4000E and XC4000X Series Field
Programmable Gate Arrays
May 14, 1999 (Version 1.6)
0
0*
Product Specification
R
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-6
May 14, 1999 (Version 1.6)
* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
Note:
All functionality in low-voltage families is the same as
in the corresponding 5-Volt family, except where numerical
references are made to timing or power.
Description
XC4000 Series devices are implemented with a regular,
flexible, programmable architecture of Configurable Logic
Blocks (CLBs), interconnected by a powerful hierarchy of
versatile routing resources, and surrounded by a perimeter
of programmable Input/Output Blocks (IOBs). They have
generous routing resources to accommodate the most
complex interconnect patterns.
The devices are customized by loading configuration data
into internal memory cells. The FPGA can either actively
read its configuration data from an external serial or
byte-parallel PROM (master modes), or the configuration
data can be written into the FPGA from an external device
(slave and peripheral modes).
XC4000 Series FPGAs are supported by powerful and
sophisticated software, covering every aspect of design
from schematic or behavioral entry, floor planning, simula-
tion, automatic block placement and routing of intercon-
nects, to the creation, downloading, and readback of the
configuration bit stream.
Because Xilinx FPGAs can be reprogrammed an unlimited
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hard-
ware must be adapted to different user applications.
FPGAs are ideal for shortening design and development
cycles, and also offer a cost-effective solution for produc-
tion rates well beyond 5,000 systems per month. For lowest
high-volume unit cost, a design can first be implemented in
the XC4000E or XC4000X, then migrated to one of Xilinx’
compatible HardWire mask-programmed devices.
Taking Advantage of Re-configuration
FPGA devices can be re-configured to change logic func-
tion while resident in the system. This capability gives the
system designer a new degree of freedom not available
with any other type of logic.
Hardware can be changed as easily as software. Design
updates or modifications are easy, and can be made to
products already in the field. An FPGA can even be re-con-
figured dynamically to perform different functions at differ-
ent times.
Re-configurable logic can be used to implement system
self-diagnostics, create systems capable of being re-con-
figured for different environments or operations, or imple-
ment multi-purpose hardware for a given application. As an
added benefit, using re-configurable FPGA devices simpli-
fies hardware design and debugging and shortens product
time-to-market.
Table 1: XC4000E and XC4000X Series Field Programmable Gate Arrays
Device
Logic
Cells
Max Logic
Gates
(No RAM)
Max. RAM
Bits
(No Logic)
Typical
Gate Range
(Logic and RAM)*
CLB
Matrix
Total
CLBs
Number
of
Flip-Flops
Max.
User I/O
XC4002XL
152
1,600
2,048
1,000 - 3,000
8 x 8
64
256
64
XC4003E
238
3,000
3,200
2,000 - 5,000
10 x 10
100
360
80
XC4005E/XL
466
5,000
6,272
3,000 - 9,000
14 x 14
196
616
112
XC4006E
608
6,000
8,192
4,000 - 12,000
16 x 16
256
768
128
XC4008E
770
8,000
10,368
6,000 - 15,000
18 x 18
324
936
144
XC4010E/XL
950
10,000
12,800
7,000 - 20,000
20 x 20
400
1,120
160
XC4013E/XL
1368
13,000
18,432
10,000 - 30,000
24 x 24
576
1,536
192
XC4020E/XL
1862
20,000
25,088
13,000 - 40,000
28 x 28
784
2,016
224
XC4025E
2432
25,000
32,768
15,000 - 45,000
32 x 32
1,024
2,560
256
XC4028EX/XL
2432
28,000
32,768
18,000 - 50,000
32 x 32
1,024
2,560
256
XC4036EX/XL
3078
36,000
41,472
22,000 - 65,000
36 x 36
1,296
3,168
288
XC4044XL
3800
44,000
51,200
27,000 - 80,000
40 x 40
1,600
3,840
320
XC4052XL
4598
52,000
61,952
33,000 - 100,000
44 x 44
1,936
4,576
352
XC4062XL
5472
62,000
73,728
40,000 - 130,000
48 x 48
2,304
5,376
384
XC4085XL
7448
85,000
100,352
55,000 - 180,000
56 x 56
3,136
7,168
448
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May 14, 1999 (Version 1.6)
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XC4000E and XC4000X Series Field Programmable Gate Arrays
6
XC4000E and XC4000X Series
Compared to the XC4000
For readers already familiar with the XC4000 family of Xil-
inx Field Programmable Gate Arrays, the major new fea-
tures in the XC4000 Series devices are listed in this
section. The
biggest
advantages
of
XC4000E
and
XC4000X devices are significantly increased system
speed, greater capacity, and new architectural features,
particularly Select-RAM memory.
The XC4000X devices
also offer many new routing features, including special
high-speed clock buffers that can be used to capture input
data with minimal delay.
Any XC4000E device is pinout- and bitstream-compatible
with the corresponding XC4000 device. An existing
XC4000 bitstream can be used to program an XC4000E
device. However, since the XC4000E includes many new
features, an XC4000E bitstream cannot be loaded into an
XC4000 device.
XC4000X Series devices are not bitstream-compatible with
equivalent array size devices in the XC4000 or XC4000E
families. However, equivalent array size devices, such as
the XC4025, XC4025E, XC4028EX, and XC4028XL, are
pinout-compatible.
Improvements in XC4000E and XC4000X
Increased System Speed
XC4000E and XC4000X devices can run at synchronous
system clock rates of up to 80 MHz, and internal perfor-
mance can exceed 150 MHz. This increase in performance
over the previous families stems from improvements in both
device processing and system architecture.
XC4000
Series devices use a sub-micron multi-layer metal process.
In addition, many architectural improvements have been
made, as described below.
The XC4000XL family is a high performance 3.3V family
based on 0.35
µ
SRAM technology and supports system
speeds to 80 MHz.
PCI Compliance
XC4000 Series -2 and faster speed grades are fully PCI
compliant. XC4000E and XC4000X devices can be used to
implement a one-chip PCI solution.
Carry Logic
The speed of the carry logic chain has increased dramati-
cally. Some parameters, such as the delay on the carry
chain through a single CLB (T
BYP
), have improved by as
much as 50% from XC4000 values. See
for more information.
Select-RAM Memory: Edge-Triggered, Synchro-
nous RAM Modes
The RAM in any CLB can be configured for synchronous,
edge-triggered, write operation. The read operation is not
affected by this change to an edge-triggered write.
Dual-Port RAM
A separate option converts the 16x2 RAM in any CLB into a
16x1 dual-port RAM with simultaneous Read/Write.
The function generators in each CLB can be configured as
either level-sensitive (asynchronous) single-port RAM,
edge-triggered (synchronous) single-port RAM, edge-trig-
gered (synchronous) dual-port RAM, or as combinatorial
logic.
Configurable RAM Content
The RAM content can now be loaded at configuration time,
so that the RAM starts up with user-defined data.
H Function Generator
In current XC4000 Series devices, the H function generator
is more versatile than in the original XC4000. Its inputs can
come not only from the F and G function generators but
also from up to three of the four control input lines. The H
function generator can thus be totally or partially indepen-
dent of the other two function generators, increasing the
maximum capacity of the device.
IOB Clock Enable
The two flip-flops in each IOB have a common clock enable
input, which through configuration can be activated individ-
ually for the input or output flip-flop or both. This clock
enable operates exactly like the EC pin on the XC4000
CLB. This new feature makes the IOBs more versatile, and
avoids the need for clock gating.
Output Drivers
The output pull-up structure defaults to a TTL-like
totem-pole. This driver is an n-channel pull-up transistor,
pulling to a voltage one transistor threshold below Vcc, just
like the XC4000 family outputs. Alternatively, XC4000
Series devices can be globally configured with CMOS out-
puts, with p-channel pull-up transistors pulling to Vcc. Also,
the configurable pull-up resistor in the XC4000 Series is a
p-channel transistor that pulls to Vcc, whereas in the origi-
nal XC4000 family it is an n-channel transistor that pulls to
a voltage one transistor threshold below Vcc.
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XC4000E and XC4000X Series Field Programmable Gate Arrays
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May 14, 1999 (Version 1.6)
Input Thresholds
The input thresholds of 5V devices can be globally config-
ured for either TTL (1.2 V threshold) or CMOS (2.5 V
threshold), just like XC2000 and XC3000 inputs. The two
global adjustments of input threshold and output level are
independent of each other. The XC4000XL family has an
input threshold of 1.6V, compatible with both 3.3V CMOS
and TTL levels.
Global Signal Access to Logic
There is additional access from global clocks to the F and
G function generator inputs.
Configuration Pin Pull-Up Resistors
During configuration, these pins have weak pull-up resis-
tors. For the most popular configuration mode, Slave
Serial, the mode pins can thus be left unconnected. The
three mode inputs can be individually configured with or
without weak pull-up or pull-down resistors. A pull-down
resistor value of 4.7 k
Ω
is recommended.
The three mode inputs can be individually configured with
or without weak pull-up or pull-down resistors after configu-
ration.
The PROGRAM input pin has a permanent weak pull-up.
Soft Start-up
Like the XC3000A, XC4000 Series devices have “Soft
Start-up.” When the configuration process is finished and
the device starts up, the first activation of the outputs is
automatically slew-rate limited. This feature avoids poten-
tial ground bounce when all outputs are turned on simulta-
neously. Immediately after start-up, the slew rate of the
individual outputs is, as in the XC4000 family, determined
by the individual configuration option.
XC4000 and XC4000A Compatibility
Existing XC4000 bitstreams can be used to configure an
XC4000E device. XC4000A bitstreams must be recompiled
for use with the XC4000E due to improved routing
resources, although the devices are pin-for-pin compatible.
Additional Improvements in XC4000X Only
Increased Routing
New interconnect in the XC4000X includes twenty-two
additional vertical lines in each column of CLBs and twelve
new horizontal lines in each row of CLBs. The twelve “Quad
Lines” in each CLB row and column include optional repow-
ering buffers for maximum speed. Additional high-perfor-
mance routing near the IOBs enhances pin flexibility.
Faster Input and Output
A fast, dedicated early clock sourced by global clock buffers
is available for the IOBs. To ensure synchronization with the
regular global clocks, a Fast Capture latch driven by the
early clock is available. The input data can be initially
loaded into the Fast Capture latch with the early clock, then
transferred to the input flip-flop or latch with the low-skew
global clock. A programmable delay on the input can be
used to avoid hold-time requirements. See
Latch Capability in CLBs
Storage elements in the XC4000X CLB can be configured
as either flip-flops or latches. This capability makes the
FPGA highly synthesis-compatible.
IOB Output MUX From Output Clock
A multiplexer in the IOB allows the output clock to select
either the output data or the IOB clock enable as the output
to the pad. Thus, two different data signals can share a sin-
gle output pad, effectively doubling the number of device
outputs without requiring a larger, more expensive pack-
age. This multiplexer can also be configured as an
AND-gate to implement a very fast pin-to-pin path. See
Additional Address Bits
Larger devices require more bits of configuration data. A
daisy chain of several large XC4000X devices may require
a PROM that cannot be addressed by the eighteen address
bits supported in the XC4000E. The XC4000X Series
therefore extends the addressing in Master Parallel config-
uration mode to 22 bits.
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May 14, 1999 (Version 1.6)
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XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Detailed Functional Description
XC4000 Series devices achieve high speed through
advanced semiconductor technology and improved archi-
tecture. The XC4000E and XC4000X support system clock
rates of up to 80 MHz and internal performance in excess
of 150 MHz. Compared to older Xilinx FPGA families,
XC4000 Series devices are more powerful. They offer
on-chip edge-triggered and dual-port RAM, clock enables
on I/O flip-flops, and wide-input decoders. They are more
versatile in many applications, especially those involving
RAM. Design cycles are faster due to a combination of
increased routing resources and more sophisticated soft-
ware.
Basic Building Blocks
Xilinx user-programmable gate arrays include two major
configurable elements: configurable logic blocks (CLBs)
and input/output blocks (IOBs).
•
CLBs provide the functional elements for constructing
the user’s logic.
•
IOBs provide the interface between the package pins
and internal signal lines.
Three other types of circuits are also available:
•
3-State buffers (TBUFs) driving horizontal longlines are
associated with each CLB.
•
Wide edge decoders are available around the periphery
of each device.
•
An on-chip oscillator is provided.
Programmable interconnect resources provide routing
paths to connect the inputs and outputs of these config-
urable elements to the appropriate networks.
The functionality of each circuit block is customized during
configuration by programming internal static memory cells.
The values stored in these memory cells determine the
logic functions and interconnections implemented in the
FPGA. Each of these available circuits is described in this
section.
Configurable Logic Blocks (CLBs)
Configurable Logic Blocks implement most of the logic in
an FPGA. The principal CLB elements are shown in
. Two 4-input function generators (F and G) offer
unrestricted versatility. Most combinatorial logic functions
need four or fewer inputs. However, a third function gener-
ator (H) is provided. The H function generator has three
inputs. Either zero, one, or two of these inputs can be the
outputs of F and G; the other input(s) are from outside the
CLB. The CLB can, therefore, implement certain functions
of up to nine variables, like parity check or expand-
able-identity comparison of two sets of four inputs.
Each CLB contains two storage elements that can be used
to store the function generator outputs. However, the stor-
age elements and function generators can also be used
independently. These storage elements can be configured
as flip-flops in both XC4000E and XC4000X devices; in the
XC4000X they can optionally be configured as latches. DIN
can be used as a direct input to either of the two storage
elements. H1 can drive the other through the H function
generator. Function generator outputs can also drive two
outputs independent of the storage element outputs. This
versatility increases logic capacity and simplifies routing.
Thirteen CLB inputs and four CLB outputs provide access
to the function generators and storage elements. These
inputs and outputs connect to the programmable intercon-
nect resources outside the block.
Function Generators
Four independent inputs are provided to each of two func-
tion generators (F1 - F4 and G1 - G4). These function gen-
erators, with outputs labeled F’ and G’, are each capable of
implementing any arbitrarily defined Boolean function of
four inputs. The function generators are implemented as
memory look-up tables. The propagation delay is therefore
independent of the function implemented.
A third function generator, labeled H’, can implement any
Boolean function of its three inputs. Two of these inputs can
optionally be the F’ and G’ functional generator outputs.
Alternatively, one or both of these inputs can come from
outside the CLB (H2, H0). The third input must come from
outside the block (H1).
Signals from the function generators can exit the CLB on
two outputs. F’ or H’ can be connected to the X output. G’ or
H’ can be connected to the Y output.
A CLB can be used to implement any of the following func-
tions:
•
any function of up to four variables, plus any second
function of up to four unrelated variables, plus any third
function of up to three unrelated variables
1
•
any single function of five variables
•
any function of four variables together with some
functions of six variables
•
some functions of up to nine variables.
Implementing wide functions in a single block reduces both
the number of blocks required and the delay in the signal
path, achieving both increased capacity and speed.
The versatility of the CLB function generators significantly
improves system speed. In addition, the design-software
tools can deal with each function generator independently.
This flexibility improves cell usage.
1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two
unregistered function generator outputs are available from the CLB.
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XC4000E and XC4000X Series Field Programmable Gate Arrays
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May 14, 1999 (Version 1.6)
Flip-Flops
The CLB can pass the combinatorial output(s) to the inter-
connect network, but can also store the combinatorial
results or other incoming data in one or two flip-flops, and
connect their outputs to the interconnect network as well.
The two edge-triggered D-type flip-flops have common
clock (K) and clock enable (EC) inputs. Either or both clock
inputs can also be permanently enabled. Storage element
functionality is described in
Latches (XC4000X only)
The CLB storage elements can also be configured as
latches. The two latches have common clock (K) and clock
enable (EC) inputs. Storage element functionality is
described in
.
Clock Input
Each flip-flop can be triggered on either the rising or falling
clock edge. The clock pin is shared by both storage ele-
ments. However, the clock is individually invertible for each
storage element. Any inverter placed on the clock input is
automatically absorbed into the CLB.
Clock Enable
The clock enable signal (EC) is active High. The EC pin is
shared by both storage elements. If left unconnected for
either, the clock enable for that storage element defaults to
the active state. EC is not invertible within the CLB.
LOGIC
FUNCTION
OF
G1-G4
G4
G3
G2
G1
G'
LOGIC
FUNCTION
OF
F1-F4
F4
F3
F2
F1
F'
LOGIC
FUNCTION
OF
F', G',
AND
H1
H'
DIN
F'
G'
H'
DIN
F'
G'
H'
G'
H'
H'
F'
S/R
CONTROL
D
EC
RD
Bypass
Bypass
SD
YQ
XQ
Q
S/R
CONTROL
D
EC
RD
SD
Q
1
1
K
(CLOCK)
Multiplexer Controlled
by Configuration Program
Y
X
DIN/H2
H1
SR/H0
EC
X6692
C1 • • • C4
4
Figure 1: Simplified Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown)
Table 2: CLB Storage Element Functionality
(active rising edge is shown)
Mode
K
EC
SR
D
Q
Power-Up or
GSR
X
X
X
X
SR
Flip-Flop
X
X
1
X
SR
__/
1*
0*
D
D
0
X
0*
X
Q
Latch
1
1*
0*
X
Q
0
1*
0*
D
D
Both
X
0
0*
X
Q
Legend:
X
__/
SR
0*
1*
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
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May 14, 1999 (Version 1.6)
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XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Set/Reset
An asynchronous storage element input (SR) can be con-
figured as either set or reset. This configuration option
determines the state in which each flip-flop becomes oper-
ational after configuration. It also determines the effect of a
Global Set/Reset pulse during normal operation, and the
effect of a pulse on the SR pin of the CLB. All three
set/reset functions for any single flip-flop are controlled by
the same configuration data bit.
The set/reset state can be independently specified for each
flip-flop. This input can also be independently disabled for
either flip-flop.
The set/reset state is specified by using the INIT attribute,
or by placing the appropriate set or reset flip-flop library
symbol.
SR is active High. It is not invertible within the CLB.
Global Set/Reset
A separate Global Set/Reset line (not shown in
)
sets or clears each storage element during power-up,
re-configuration, or when a dedicated Reset net is driven
active. This global net (GSR) does not compete with other
routing resources; it uses a dedicated distribution network.
Each flip-flop is configured as either globally set or reset in
the same way that the local set/reset (SR) is specified.
Therefore, if a flip-flop is set by SR, it is also set by GSR.
Similarly, a reset flip-flop is reset by both SR and GSR.
GSR can be driven from any user-programmable pin as a
global reset input. To use this global net, place an input pad
and input buffer in the schematic or HDL code, driving the
GSR pin of the STARTUP symbol. (See
cific pin location can be assigned to this input using a LOC
attribute or property, just as with any other user-program-
mable pad. An inverter can optionally be inserted after the
input buffer to invert the sense of the Global Set/Reset sig-
nal.
Alternatively, GSR can be driven from any internal node.
Data Inputs and Outputs
The source of a storage element data input is programma-
ble. It is driven by any of the functions F’, G’, and H’, or by
the Direct In (DIN) block input. The flip-flops or latches drive
the XQ and YQ CLB outputs.
Two fast feed-through paths are available, as shown in
. A two-to-one multiplexer on each of the XQ and
YQ outputs selects between a storage element output and
any of the control inputs. This bypass is sometimes used by
the automated router to repower internal signals.
Control Signals
Multiplexers in the CLB map the four control inputs (C1 - C4
in
) into the four internal control signals (H1,
DIN/H2, SR/H0, and EC). Any of these inputs can drive any
of the four internal control signals.
When the logic function is enabled, the four inputs are:
•
EC — Enable Clock
•
SR/H0 — Asynchronous Set/Reset or H function
generator Input 0
•
DIN/H2 — Direct In or H function generator Input 2
•
H1 — H function generator Input 1.
When the memory function is enabled, the four inputs are:
•
EC — Enable Clock
•
WE — Write Enable
•
D0 — Data Input to F and/or G function generator
•
D1 — Data input to G function generator (16x1 and
16x2 modes) or 5th Address bit (32x1 mode).
Using FPGA Flip-Flops and Latches
The abundance of flip-flops in the XC4000 Series invites
pipelined designs. This is a powerful way of increasing per-
formance by breaking the function into smaller subfunc-
tions and executing them in parallel, passing on the results
through pipeline flip-flops. This method should be seriously
considered wherever throughput is more important than
latency.
To include a CLB flip-flop, place the appropriate library
symbol. For example, FDCE is a D-type flip-flop with clock
enable and asynchronous clear. The corresponding latch
symbol (for the XC4000X only) is called LDCE.
In XC4000 Series devices, the flip flops can be used as reg-
isters or shift registers without blocking the function gener-
ators from performing a different, perhaps unrelated task.
This ability increases the functional capacity of the devices.
The CLB setup time is specified between the function gen-
erator inputs and the clock input K. Therefore, the specified
CLB flip-flop setup time includes the delay through the
function generator.
Using Function Generators as RAM
Optional modes for each CLB make the memory look-up
tables in the F’ and G’ function generators usable as an
array of Read/Write memory cells. Available modes are
level-sensitive
(similar
to
the
XC4000/A/H
families),
edge-triggered, and dual-port edge-triggered. Depending
on the selected mode, a single CLB can be configured as
either a 16x2, 32x1, or 16x1 bit array.
PAD
IBUF
GSR
GTS
CLK DONEIN
Q1Q4
Q2
Q3
STARTUP
X5260
Figure 2: Schematic Symbols for Global Set/Reset
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-12
May 14, 1999 (Version 1.6)
Supported CLB memory configurations and timing modes
for single- and dual-port modes are shown in
.
XC4000 Series devices are the first programmable logic
devices with edge-triggered (synchronous) and dual-port
RAM accessible to the user.
Edge-triggered RAM simpli-
fies system timing. Dual-port RAM doubles the effective
throughput of FIFO applications. These features can be
individually programmed in any XC4000 Series CLB.
Advantages of On-Chip and Edge-Triggered RAM
The on-chip RAM is extremely fast. The read access time is
the same as the logic delay.
The write access time is
slightly slower.
Both access times are much faster than
any off-chip solution, because they avoid I/O delays.
Edge-triggered RAM, also called synchronous RAM, is a
feature never before available in a Field Programmable
Gate Array. The simplicity of designing with edge-triggered
RAM, and the markedly higher achievable performance,
add up to a significant improvement over existing devices
with on-chip RAM.
Three application notes are available from Xilinx that dis-
cuss edge-triggered RAM: “
XC4000E Edge-Triggered and
Dual-Port
RAM
Capability,”
“
Implementing
FIFOs
in
XC4000E RAM,” and “Synchronous and Asynchronous
FIFO Designs.” All three application notes apply to both
XC4000E and XC4000X RAM.
RAM Configuration Options
The function generators in any CLB can be configured as
RAM arrays in the following sizes:
•
Two 16x1 RAMs: two data inputs and two data outputs
with identical or, if preferred, different addressing for
each RAM
•
One 32x1 RAM: one data input and one data output.
One F or G function generator can be configured as a 16x1
RAM while the other function generators are used to imple-
ment any function of up to 5 inputs.
Additionally, the XC4000 Series RAM may have either of
two timing modes:
•
Edge-Triggered (Synchronous): data written by the
designated edge of the CLB clock. WE acts as a true
clock enable.
•
Level-Sensitive (Asynchronous): an external WE signal
acts as the write strobe.
The selected timing mode applies to both function genera-
tors within a CLB when both are configured as RAM.
The number of read ports is also programmable:
•
Single Port: each function generator has a common
read and write port
•
Dual Port: both function generators are configured
together as a single 16x1 dual-port RAM with one write
port and two read ports. Simultaneous read and write
operations to the same or different addresses are
supported.
RAM configuration options are selected by placing the
appropriate library symbol.
Choosing a RAM Configuration Mode</