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4800 Great America Parkway Ste 202

Tel: 408-235-8680

Santa Clara, CA. 95054

Fax: 408-235-8685

Preliminary

EN27LV010 / EN27LV010B

FEATURES

•

Read Access Time

90ns,

120ns,

150ns, -200ns

•

Single +3.3V Power Supply

-Regulated power supply 3.0V - 3.6V

(EN27LV010

)

-Unregulated power supply 2.7V - 3.6V

(

EN27LV010B for battery operated systems)

•

Programming Voltage +12.75V

•

QuikRite

Programming Algorithm

•

Typical programming time 20

•

Low Power CMOS Operation

•

A Standby (Typical)

•

15mA Operation (Max.)

•

CMOS- and TTL-Compatible I/O

•

High-Reliability CMOS Technology

•

Latch-Up Immunity to 100mA

from -1V to V

+ 1V

•

Two-Line Control (

)

•

Standard Product Identification Code

•

JEDEC Standard Pinout

•

32-pin PDIP

•

32-pin PLCC

•

32-pin TSOP (Type 1)

•

Commercial and Industrial Temperature

Ranges

GENERAL DESCRIPTION

The EN27LV010/EN27LV010B is a low-voltage, low-power 1-Megabit, 3.3V one-time-

programmable (OTP) read-only memory (EPROM). Organized into 128K words with 8 bits per

word, it features QuikRite

single-address location programming, typically at 20

s per byte. Any

byte can be accessed in less than 90ns. The EN27LV010/EN27LV010B has separate Output

Enable (

) and Chip Enable (

) controls which eliminate bus contention issues. The

EN27LV010 has a Vcc tolerance range of 3.0V to 3.6 V, making it suitable for use in systems that

have regulated power supplies. The EN27LV010B has a Vcc tolerance range of 2.7 V to 3.6V,

making it an ideal device for battery operated systems.

FIGURE 1. PDIP

Pin Name

Function

A0-A16

Addresses

DQ0-DQ7

Outputs

Chip Enable

Output Enable

PGM

Program Strobe

No Connect

PDIP Top View

VPP

A16

A15

A12

DQ0

DQ1

DQ2

VSS

VCC

PGM

A14

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

EN27LV010/EN27LV010B

1Megabit Low Voltage

EPROM (128K x 8)

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Preliminary

EN27LV010 / EN27LV010B

FIGURE 4. BLOCK DIAGRAM

PGM

A0-A16

ADDRESS

INPUTS

CONTROL

LOGIC

VCC

VSS

VPP

INPUT/

OUTPUT

BUFFERS

DQ0 - DQ7

1024

Y-DECODER

Y-SELECT

X-DECODER

1M BIT

CELL

MATRIX

1024

FUNCTIONAL DESCRIPTION

THE QUIKRITE

PROGRAMMING OF THE EN27LV010/EN27LV010B

When the EN27LV010/EN27LV010B is delivered, the chip has all 1M bits in the “ONE”, or

HIGH state. “ZEROs” are loaded into the EN27LV010/EN27LV010B through the procedure of

programming.

The programming mode is entered when 12.75

0.25V is applied to the V

pin,

is at V

, and

and

PGM

are at V

. For programming, the data to be programmed is applied with

8 bits in parallel to the data pins.

The QUIKRITE

programming flowchart in Figure 5 shows Eon’s interactive programming

algorithm. The interactive algorithm reduces programming time by using 20

s to 100

programming pulses and giving each address only as many pulses as is necessary in order to

reliably program the data. After each pulse is applied to a given address, the data in that

address is verified. If the data is not verified, additional pulses are given until it is verified or

until the maximum number of pulses is reached. This process is repeated while sequencing

through each address of the EN27LV010/EN27LV010B. This part of the programming

algorithm is done at V

= 6.25V to assure that each EPROM bit is programmed to a

sufficiently high threshold voltage. This ensures that all bits have sufficient margin. After the

final address is completed, the entire EPROM memory is read at V

= V

= 5.25

0.25V to

verify the entire memory. EN27LV010 / EN27LV010B can be programmed using the same

programming algorithm as the 5V Read EPROM EN27C010.

4800 Great America Parkway Ste 202

Tel: 408-235-8680

Santa Clara, CA. 95054

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Preliminary

EN27LV010 / EN27LV010B

PROGRAM INHIBIT MODE

Programming of multiple EN27LV010/EN27LV010B in parallel with different data is also easily

accomplished by using the Program Inhibit Mode. Except for

, all like inputs of the parallel

EN27LV010/EN27LV010B may be common. A TTL low-level program pulse applied to an

EN27LV010/EN27LV010B

input with V

= 12.75

0.25V,

PGM

LOW, and

HIGH

will program that EN27LV010/EN27LV010B. A high-level

input inhibits the other

EN27LV010/EN27LV010B from being programmed.

PROGRAM VERIFY MODE

Verification should be performed on the programmed bits to determining that they were

correctly programmed. The verification should be performed with

and

at V

PGM

, and V

at its programming voltage.

AUTO PRODUCT IDENTIFICATION

The Auto Product Identification mode allows the reading out of a binary code from an EPROM that

will identify its manufacturer and type. This mode is intended for use by programming equipment

for the purpose of automatically matching the device to be programmed with its corresponding

programming algorithm. This mode is functional in the 25

C ambient temperature range

that is required when programming the EN27LV010/EN27LV010B.

To activate this mode, the programming equipment must force 12.0 V

0.5V on address line A9

of the EN27LV010/EN27LV010B. Two identifier bytes may then be sequenced from the device

outputs by toggling address line A0 from V

to V

, when A1 = V

. All other address lines must

be held at V

during Auto Product Identification mode.

Byte 0 (A0 = V

) represents the manufacturer code, and byte 1 (A0 = V

), the device code. For

the EN27LV010/EN27LV010B, these two identifiers bytes are given in the Mode Select Table. All

identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined

as the parity bit.

When A1 = V

, the EN27LV010/EN27LV010B will read out the binary code of

7F, continuation code, to signify the unavailability of manufacturer ID codes.

4800 Great America Parkway Ste 202

Tel: 408-235-8680

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Preliminary

EN27LV010 / EN27LV010B

READ MODE

The EN27LV010/EN27LV010B has two control functions, both of which must be logically

satisfied in order to obtain data at the outputs. Chip Enable (

) is the power control and

should be used for device selection. Output Enable (

) is the output control and should be

used to gate data to the output pins, independent of device selection. Assuming that

addresses are stable, address access time (t

ACC

) is equal to the delay from

to output

). Data is available at the outputs (t

) after the falling edge of

, assuming the

has

been LOW and addresses have been stable for at least t

ACC

- t

STANDBY MODE

The EN27LV010/EN27LV010B has CMOS standby mode which reduces the maximum V

current to 10

A. It is placed in CMOS standby when

is at V

0.3 V. The

EN27LV010/EN27LV010B also has a TTL-standby mode which reduces the maximum V

current to 0.6 mA. It is placed in TTL-standby when

is at V

. When in standby mode,

the outputs are in a high-impedance state, independent of the

input.

TWO-LINE OUTPUT CONTROL FUNCTION

To accommodate multiple memory connections, a two-line control function is provided to allow

for:

1. Low memory power dissipation,

2. Assurance that output bus contention will not occur.

It is recommended that

be decoded and used as the primary device-selection function,

while

be made a common connection to all devices in the array and connected to the READ

line from the system control bus. This assures that all deselected memory devices are in their

low-power standby mode and that the output pins are only active when data is desired from a

particular memory device.

SYSTEM CONSIDERATIONS

During the switch between active and standby conditions, transient current peaks are produced

on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks

is dependent on the output capacitance loading of the device. At a minimum, a 0.1

F ceramic

capacitor (high frequency, low inherent inductance) should be used on each device between

VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused

by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7

F bulk

electrolytic capacitor should be used between V

and V

for each eight devices. The location

of the capacitor should be close to where the power supply is connected to the array.

4800 Great America Parkway Ste 202

Tel: 408-235-8680

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Preliminary

EN27LV010 / EN27LV010B

MODE SELECT TABLE

Mode

PGM

Output

Read

(2)

OUT

Output Disable

High Z

Standby (TTL)

High Z

Standby (CMOS)

0.3V

High Z

Program

(4)

Program Verify

OUT

Program Inhibit

High Z

Manufacturer Code

(3)

(1)

Device Code

(3)

(1)

NOTES:

1) VH = 12.0V

0.5V

2) X = Either V

or V

3) For Manufacturer Code and Device Code, A1 = V

When A1 = V

, both codes will read 7F

4) See DC Programming Characteristics for V

voltage during programming

EON’S STANDARD PRODUCT IDENTIFICATION CODE

Pins

Hex

Data

Code

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

Manufacturer

Device Type

Continuation

4800 Great America Parkway Ste 202

Tel: 408-235-8680

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Fax: 408-235-8685

Preliminary

EN27LV010 / EN27LV010B

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

-65

C to +125

Ambient Temperature

with Power Applied

-40

C to +85

Voltage with Respect to V

All pins except A9, V

, V

-0.6V to V

+ 0.5V

A9, V

-0.6V to +13.5V

-0.6V to +7.0V

OPERATING RANGES

Commercial (C)

Case Temperature(Tc)

C to +70

Industrial (I)

Case Temperature(Tc)

-40

C to +85

Supply READ Voltages

(for battery operated systems)

+3.0V to +3.6V

+2.7V to +3.6V

(Functionality is guaranteed between these limits)

Stresses above those shown above may cause permanent damage to the device. This is a stress rating only and

operation above these specifications for extended periods may affect device reliability. Operation outside the

"OPERATING RANGES" shown above voids any and all warranty provisions.

DC CHARACTERISTICS FOR READ OPERATION

Symbol

Parameter

Min.

Max.

Unit

Conditions

Output High Voltage

2.4

= -2.0mA

Output Low Voltage

0.45

= 2.0mA

Input High Voltage

2.0

+0.5

Input Low Voltage

-0.3

0.8

Input Leakage Current

-5

= 0 to 3.6V

Output Leakage Current

-10

OUT

= 0 to 3.6V

CC3

Power -Down Current

CE = V

0.3V

CC2

Standby Current

0.6

CE = V

CC1

Active Current

CE = V

, f=5MHz,

OUT

= 0mA

PP1

Supply Current Read

100

CE = OE = V

= 3.6V

CAPACITANCE

Symbol

Parameter

Typ.

Max.

Unit

Conditions

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

VPP

Capacitance

= 0V

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Preliminary

EN27LV010 / EN27LV010B

AC CHARACTERISTICS FOR READ OPERATION

EN27LV010

EN27LV010B

-90

-120

-150

-200

Symbol

Parameter

Condition

Min

Max

Min

Max

Min

Max

Min

Max

Unit

tACC (3)

Address to

Output Delay

CE = OE =

120

150

200

tCE (2)

CE to Output

Delay

OE = V

120

150

200

tOE (2, 3)

OE to Output

Delay

OE = V

tDF (4, 5)

OE or CE High to Output Float,

whichever occurred first

tOH

Output Hold from Address,

or OE , whichever occurred first

Note: Please contact Marketing Department for other speed requirements.

FIGURE 6. AC WAVEFORMS FOR READ OPERATION

ADDRESS

ADDRESS VALID

OUTPUT

VALID

tCE

tACC

HIGH Z

tOE

tDF

tOH

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Preliminary

EN27LV010 / EN27LV010B

FIGURE 7: TEST WAVEFORMS AND MEASUREMENTS

DC PROGRAMMING CHARACTERISTICS

Test

Limits

Symbol

Parameter

Conditions

Min.

Max

Units

Input Load Current

IN =

IL,

5.0

Input Low Level

-0.5

0.8

Input High Level

0.7 V

+ 0.5

Output Low Voltage

OL =

2.0 mA

0.45

Output High Voltage

OH =

400 µA

2.4

ccp

Supply Current

PP2

Supply Current

CE = PGM = V

IL,

A9 Product Identification Voltage

11.5

12.5

Quikrite Supply Voltage

6.0

6.5

Quikrite Programming Voltage

12.5

13.0

Input Test Waveform and Measurement Level

Output Test Load