EN27LV512 / EN27LV512B
4800 Great America Parkway Ste 202
Tel: 408-235-8680
Santa Clara, CA. 95054
Fax: 408-235-8685
Preliminary
1
FEATURES
•
Read Access Time
:
-90ns, -120ns, -150ns, -200ns
•
Single +3.3V Power Supply
-Regulated power supply 3.0V - 3.6V
(EN27LV512)
-Unregulated power supply 2.7V - 3.6 V
(EN27LV512B for battery operated systems)
•
Programming Voltage +12.75V
•
QuikRite
TM
Programming Algorithm
•
Typical programming time 20
µ
s
•
Low Power CMOS Operation
•
1
µ
A Standby (Typical)
•
15mA Operation (Max.)
•
CMOS- and TTL-Compatible I/O
•
High-Reliability CMOS Technology
•
Latch-Up Immunity to 100mA
from -1V to V
CC
+ 1V
•
Two-Line Control (
OE
&
CE
)
•
Standard Product Identification Code
•
JEDEC Standard Pinout
•
28-pin PDIP
•
32-pin PLCC
•
28-pin TSOP (Type 1)
•
Commercial and Industrial Temperature
Ranges
GENERAL DESCRIPTION
The EN27LV512 / EN27LV512B is a low voltage, low-power 512K bit, 3.3V one-time-
programmable (OTP) read-only memory (EPROM). Organized into 64K words with 8 bits per
word, it features QuikRite
TM
single-address location programming, typically at 20
µ
s per byte. Any
byte can be accessed in less than 90ns. The EN27LV512 / EN27LV512B has separate Output
Enable (
OE
) and Chip Enable (
CE
) controls which eliminate bus contention issues. The
EN27LV512 has a Vcc tolerance range of 3.0V to 3.6V, making it suitable for use in systems that
have regulated power supplies. The EN27LV512B has a Vcc tolerance range of 2.7V to 3.6V,
making it ideally suited for battery operated systems.
FIGURE 1. PDIP
Pin Name
Function
A0-A15
Addresses
DQ0-DQ7
Outputs
CE
Chip Enable
OE
Output Enable
NC
No Connect
EN27LV512 / EN27LV512B 512KBIT EPROM (64K x 8)
EN27LV512 / EN27LV512B
4800 Great America Parkway Ste 202
Tel: 408-235-8680
Santa Clara, CA. 95054
Fax: 408-235-8685
Preliminary
2
FIGURE 2. TSOP
EN27LV512 /
EN27LV512B
FIGURE 3. PLCC
Top View
EN27LV512 / EN27LV512B
4800 Great America Parkway Ste 202
Tel: 408-235-8680
Santa Clara, CA. 95054
Fax: 408-235-8685
Preliminary
3
FIGURE 4. BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
THE QUIKRITE
TM
PROGRAMMING OF THE EN27LV512 / EN27LV512B
When the EN27LV512 / EN27LV512B is delivered, the chip has all 512K bits in the “ONE”, or
HIGH state. “ZEROs” are loaded into the EN27LV512 / EN27LV512B through the procedure
of programming.
The programming mode is entered when 12.75
±
0.25V is applied to the
OE
/V
PP
pin and
CE
is at V
IL
. For programming, the data to be programmed is applied with 8 bits in parallel to
the data pins.
The QUIKRITE
TM
programming flowchart in Figure 5 shows Eon’s interactive programming
algorithm. The interactive algorithm reduces programming time by using 20
µ
s to 100
µ
s
programming pulses and giving each address only as many pulses as is necessary in order to
reliably program the data. After each pulse is applied to a given address, the data in that
address is verified. If the data is not verified, additional pulses are given until it is verified or
until the maximum number of pulses is reached. This process is repeated while sequencing
through each address of the EN27LV512 / EN27LV512B. This part of the programming
algorithm is done at V
CC
= 6.25V to assure that each EPROM bit is programmed to a
sufficiently high threshold voltage. This ensures that all bits have sufficient margin. After the
final address is completed, the entire EPROM memory is read at V
CC
= 5.25
±
0.25V to verify
the entire memory. EN27LV512 / EN27LV512B can be programmed using the same
programming algorithm as the 5V Read EPROM EN27C512.
EN27LV512 / EN27LV512B
4800 Great America Parkway Ste 202
Tel: 408-235-8680
Santa Clara, CA. 95054
Fax: 408-235-8685
Preliminary
4
PROGRAM INHIBIT MODE
Programming of multiple EN27LV512 / EN27LV512B in parallel with different data is also
easily accomplished by using the Program Inhibit Mode. Except for
CE
, all like inputs of the
parallel EN27LV512 / EN27LV512B may be common. A TTL low-level program pulse applied
to an EN27LV512 / EN27LV512B
CE
input with
OE
/V
PP
= 12.75
±
0.25V will program that
EN27LV512 / EN27LV512B. A high-level
CE
input inhibits the other EN27LV512 /
EN27LV512B from being programmed.
PROGRAM VERIFY MODE
Verification should be performed on the programmed bits to determining that they were
correctly programmed. The verification should be performed with
OE
/V
PP
and
CE
at V
IL
. Data
should be verified at
t
DV
after the falling edge of
CE
.
AUTO PRODUCT IDENTIFICATION
The Auto Product Identification mode allows the reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode is intended for use by programming equipment
for the purpose of automatically matching the device to be programmed with its corresponding
programming algorithm. This mode is functional in the 25
°
C
±
5
°
C ambient temperature range
that is required when programming the EN27LV512 / EN27LV512B.
To activate this mode, the programming equipment must force 12.0 V
±
0.5V on address line A9
of the EN27LV512 / EN27LV512B. Two identifier bytes may then be sequenced from the device
outputs by toggling address line A0 from V
IL
to V
IH
, when A1 = V
IH
. All other address lines must
be held at V
IL
during Auto Product Identification mode.
Byte 0 (A0 = V
IL
) represents the manufacturer code, and byte 1 (A0 = V
IH
), the device code. For
the EN27LV512 / EN27LV512B, these two identifiers bytes are given in the Mode Select Table.
All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7)
defined as the parity bit.
When A1 = V
IL
, the EN27LV512 / EN27LV512B will read out the binary
code of 7F, continuation code, to signify the unavailability of manufacturer ID codes.
EN27LV512 / EN27LV512B
4800 Great America Parkway Ste 202
Tel: 408-235-8680
Santa Clara, CA. 95054
Fax: 408-235-8685
Preliminary
5
READ MODE
The EN27LV512 / EN27LV512B has two control functions, both of which must be logically
satisfied in order to obtain data at the outputs. Chip Enable (
CE
) is the power control and
should be used for device selection. Output Enable (
OE
) is the output control and should be
used to gate data to the output pins, independent of device selection. Assuming that
addresses are stable, address access time (t
ACC
) is equal to the delay from
CE
to output (t
CE
).
Data is available at the outputs (t
OE
) after the falling edge of
OE
, assuming the
CE
has been
LOW and addresses have been stable for at least t
ACC
- t
OE
.
STANDBY MODE
The EN27LV512 / EN27LV512B has CMOS standby mode which reduces the maximum V
CC
current to 10
µ
A. It is placed in CMOS standby when
CE
is at V
CC
±
0.3 V. The EN27LV512 /
EN27LV512B also has a TTL-standby mode which reduces the maximum V
CC
current to
0.6 mA. It is placed in TTL-standby when
CE
is at V
IH
. When in standby mode, the outputs
are in a high-impedance state, independent of the
OE
input.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a two-line control function is provided to allow
for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not occur.
It is recommended that
CE
be decoded and used as the primary device-selection function,
while
OE
be made a common connection to all devices in the array and connected to the READ
line from the system control bus. This assures that all deselected memory devices are in their
low-power standby mode and that the output pins are only active when data is desired from a
particular memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby conditions, transient current peaks are produced
on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks
is dependent on the output capacitance loading of the device. At a minimum, a 0.1
µ
F ceramic
capacitor (high frequency, low inherent inductance) should be used on each device between Vcc
and Vss to minimize transient effects. In addition, to overcome the voltage drop caused by the
inductive effects of the printed circuit board traces on EPROM arrays, a 4.7
µ
F bulk electrolytic
capacitor should be used between Vcc and Vss for each eight devices. The location of the
capacitor should be close to where the power supply is connected to the array.
EN27LV512 / EN27LV512B
4800 Great America Parkway Ste 202
Tel: 408-235-8680
Santa Clara, CA. 95054
Fax: 408-235-8685
Preliminary
6
MODE SELECT TAB
Mode
CE
OE
/
V
PP
A0
A9
Output
Read
V
IL
V
IL
X
X
D
OUT
Output Disable
V
IL
V
IH
X
X
High Z
Standby (TTL)
V
IH
X
X
X
High Z
Standby (CMOS)
V
CC
±
0.3V
X
X
X
High Z
Program
(4)
V
IL
V
PP
X
X
D
IN
Program Verify
V
IL
V
IL
X
X
D
OUT
Program Inhibit
V
IH
V
p p
X
X
High Z
Manufacturer Code
(3)
V
IL
V
IL
V
IL
VH(1)
1C
Device Code
(3)
V
IL
V
IL
V
IH
VH
(1)
83
NOTES:
1) VH = 12.0V
±
0.5V
2) X = Either V
IH
or V
IL
3) For Manufacturer Code and Device Code, A1 = V
IH
When A1 = V
IL
, both codes will read 7F
4) See DC Programming Characteristics for V
PP
voltage during programming
EON’S STANDARD PRODUCT IDENTIFICATION CODE
Pins
Hex
Data
Code
A0
A1
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Manufacturer
0
1
0
0
0
1
1
1
0
0
1C
Device Type
1
1
1
0
0
0
0
0
1
1
83
Continuation
0
0
0
1
1
1
1
1
1
1
7F
1
0
0
1
1
1
1
1
1
1
7F
EN27LV512 / EN27LV512B
4800 Great America Parkway Ste 202
Tel: 408-235-8680
Santa Clara, CA. 95054
Fax: 408-235-8685
Preliminary
7
FIGURE 5. QUIKRITE
TM
PROGRAMMING FLOW CHART
NOTE 1: Either 100
µ
s or 20
µ
s pulse.
NOTE 1
EN27LV512 / EN27LV512B
4800 Great America Parkway Ste 202
Tel: 408-235-8680
Santa Clara, CA. 95054
Fax: 408-235-8685
Preliminary
8
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
-65
à
C to +125
à
C
Ambient Temperature
with Power Applied
-40
à
C to +85
à
C
Voltage with Respect to V
SS
All pins except A9, V
PP
, V
CC
-0.6V to V
CC
+ 0.5V
A9, V
PP
-0.6V to +13.5V
V
CC
-0.6V to +7.0V
OPERATING RANGES
Commercial (C)
Case Temperature(Tc)
0
à
C to +70
à
C
Industrial (I)
Case Temperature(Tc)
-40
à
C to +85
à
C
Supply READ Voltages
(For battery operated systems)
+3.0V to +3.6V
+2.7V to +3.6V
(Functionality is guaranteed between these limits)
Stresses above those shown above may cause permanent damage to the device. This is a stress rating only and
operation above these specifications for extended periods may affect device reliability. Operation outside the
"OPERATING RANGES" shown above voids any and all warranty provisions.
DC CHARACTERISTICS FOR READ OPERATION
Symbol
Parameter
Min.
Max.
Unit
Conditions
V
OH
Output High Voltage
2.4
V
I
OH
= -2.0mA
V
OL
Output Low Voltage
0.45
V
I
OL
= 2.0mA
V
IH
Input High Voltage
2.0
V
CC
+0.5
V
V
IL
Input Low Voltage
-0.3
0.8
V
I
LI
Input Leakage Current
-5
5
µ
A
V
IN
= 0 to 3.6V
I
LO
Output Leakage Current
-10
10
µ
A
V
OUT
= 0 to 3.6V
I
CC3
V
CC
Power -Down Current
10
µ
A
CE = V
CC
±
0.3V
I
CC2
V
CC
Standby Current
0.6
mA
CE = V
IH
I
CC1
V
CC
Active Current
15
mA
CE = V
IL
, f=5MHz,
I
OUT
= 0mA
I
PP1
V
PP
Supply Current Read
100
µ
A
CE = OE = V
IL
,
V
PP
= 3.6V
CAPACITANCE
Symbol
Parameter
Typ.
Max.
Unit
Conditions
C
IN
Input Capacitance
8
12
pF
V
IN
= 0V
C
OUT
Output Capacitance
8
12
pF
V
OUT
= 0V
C
VPP
V
PP
Capacitance
18
25
pF
V
PP
= 0V
EN27LV512 / EN27LV512B
4800 Great America Parkway Ste 202
Tel: 408-235-8680
Santa Clara, CA. 95054
Fax: 408-235-8685
Preliminary
9
AC CHARACTERISTICS FOR READ OPERATION
EN27LV512
EN27LV512B
-90
-120
-120
-150
-150
-200
-200
Symbol
Parameter
Condition
Min
Max
Min
Max
Min
Max
Min
Max
Unit
tACC (3)
Address to
Output Delay
CE = OE = V
IL
90
120
150
200
ns
tCE (2)
CE to Output
Delay
OE = V
IL
90
120
150
200
ns
tOE (2, 3)
OE to Output
Delay
OE = V
IL
45
45
50
50
ns
tDF (4, 5)
OE or CE High to Output Float,
whichever occurred first
40
40
40
40
ns
tOH
Output Hold from Address, CE
or OE , whichever occurred first
0
0
0
0
ns
FIGURE 6. AC WAVEFORMS FOR READ OPERATION
CE
ADDRESS
ADDRESS VALID
OE
OUTPUT
OUTPUT
VALID
tCE
tACC
HIGH Z
tOE
tDF
tOH
EN27LV512 / EN27LV512B
4800 Great America Parkway Ste 202
Tel: 408-235-8680
Santa Clara, CA. 95054
Fax: 408-235-8685
Preliminary
10
FIGURE 7. TEST WAVEFORMS AND MEASUREMENTS
Input Test Waveform and Measurement
Output Test Load
DC PROGRAMMING CHARACTERISTICS
Test
Limits
Symbol
Parameter
Conditions
Min.
Max
Units
I
LI
Input Load Current
V
IN =
V
IL
, V
IH
5.0
µ
A
V
IL
Input Low Level
-0.5
0.8
V
V
IH
Input High Level
0.7 V
CC
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL =
2.0 mA
0.45
V
V
OH
Output High Voltage
I
OH =
-400
µ
A
2.4
V
I
ccp
V
CC
Supply Current
40
mA
I
PP2
V
PP
Supply Current
CE
= V
IL,
10
mA
V
ID
A9 Product Identification Voltage
11.5
12.5
V
V
cc
Quikrite Supply Voltage
6.0
6.5
V
V
pp
Quikrite Programming Voltage
12.5
13.0
V
EN27LV512 / EN27LV512B
4800 Great America Parkway Ste 202
Tel: 408-235-8680
Santa Clara, CA. 95054
Fax: 408-235-8685
Preliminary
11
FIGURE 8. PROGRAMMING WAVEFORMS
EN27LV512 / EN27LV512B
4800 Great America Parkway Ste 202
Tel: 408-235-8680
Santa Clara, CA. 95054
Fax: 408-235-8685
Preliminary
12
SWITCHING PROGRAMMING CHARACTERISTICS
(T
A
= + 25
°
C
±
5
°
C)
PARAMETER
SYMBOL
STANDARD
PARAMETER DESCRIPTION
Min.
Max
Units
t
AS
Address Setup Time
2
µ
s
t
OES
OE /V
PP
Setup Time
2
µ
s
t
OEH
OE /V
PP
Hold Time
2
µ
s
t
DS
Data Setup Time
2
µ
s
t
AH
Address Hold Time
0
µ
s
t
DH
Data Hold Time
2
µ
s
t
DFP
Output Enable to Output Float Delay
0
130
ns
t
PW
PGM Program Pulse Width
20
105
µ
s
t
VCS
V
cc
Setup Time
2
µ
s
t
DV
Data Valid from CE
150
ns
t
VR
OE /V
PP
Hold Time
2
µ
s
ORDERING INFORMATION
EN27LV512 90
P
I
TEMPERATURE RANGE
(Blank) = Commercial ( 0
à
C to +70
à
C)
I = Industrial ( -40
à
C to +85
à
C)
PACKAGE
P = 28 Plastic DIP
J = 32 Plastic PLCC
T = 28 Plastic TSOP
SPEED
90 = 90ns
120 = 120ns
150 = 150ns
200 = 200ns
BASE PART NUMBER
EN = EON Silicon Devices
27 = EPROM
LV = Low Voltage CMOS
512 = 64K x 8 3.0V to 3.6V Vcc Tolerance
512B = 64K x 8 2.7V to 3.6V Vcc Tolerance