Microsoft Word - EN29F040.doc

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EN29F040

Rev. D, Issue Date: 2001/07/05

FEATURES

•

5.0V operation for read/write/erase

operations

•

Fast Read Access Time

- 45ns, 55ns, 70ns, and 90ns

•

Sector Architecture:

- 8 uniform sectors of 64Kbytes each

- Supports full chip erase

- Individual sector erase supported

- Sector protection:

Hardware locking of sectors to prevent

program or erase operations within

individual sectors

•

High performance program/erase speed

- Byte program time: 10µs typical

- Sector erase time: 500ms typical

- Chip erase time: 3.5s typical

•

Low Standby Current

- 1µA CMOS standby current-typical

- 1mA TTL standby current

•

Low Power Active Current

- 30mA active read current

- 30mA program/erase current

•

JEDEC Standard program and erase

commands

•

JEDEC standard DATA polling and toggle

bits feature

•

Single Sector and Chip Erase

•

Sector Unprotect Mode

•

Embedded Erase and Program Algorithms

•

Erase Suspend / Resume modes:

Read and program another Sector during

Erase Suspend Mode

•

0.35 µm double-metal double-poly

triple-well CMOS Flash Technology

•

Low Vcc write inhibit < 3.2V

•

100K endurance cycle

•

Package Options

- 32-pin PDIP

- 32-pin PLCC

- 32-pin TSOP (Type 1)

•

Commercial and Industrial Temperature

Ranges

GENERAL DESCRIPTION

The EN29F040 is a 4-Megabit, electrically erasable, read/write non-volatile flash memory. Organized

into 512K words with 8 bits per word, the 4M of memory is arranged in eight uniform sectors of

64Kbytes each. Any byte can be programmed typically in 10µs. The EN29F040 features 5.0V

voltage read and write operation, with access times as fast as 45ns to eliminate the need for WAIT

states in high-performance microprocessor systems.

The EN29F040 has separate Output Enable ( OE ), Chip Enable (

), and Write Enable (

W E

)

controls, which eliminate bus contention issues. This device is designed to allow either single

(or

multiple) Sector or full chip erase operation, where each Sector can be individually protected against

program/erase operations or temporarily unprotected to erase or program. The device can sustain a

minimum of 100K program/erase cycles on each Sector.

EN29F040

4 Megabit (512K x 8-bit) Flash Memory

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EN29F040

Rev. D, Issue Date: 2001/07/05

TABLE 1. PIN DESCRIPTION

FIGURE 1. LOGIC DIAGRAM

Pin Name

Function

A0-A18 Addresses

DQ0-DQ7 Data

Inputs/Outputs

Chip Enable

Output Enable

W E

Write Enable

Vcc

Supply Voltage

(5V

10% )

Vss Ground

TABLE 2. SECTOR ARCHITECTURE

Sector

ADDRESSES

SIZE (Kbytes)

A18

A17

A16

70000h - 7FFFFh

60000h - 6FFFFh

5 50000h

–

5FFFFh

1 0 1

40000h – 4FFFFh

30000h – 3FFFFh

20000h - 2FFFFh

10000h - 1FFFFh

00000h - 0FFFFh

EN29F040

DQ0 - DQ7

A0 - A18

Vcc

Vss

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EN29F040

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TABLE 3. OPERATING MODES

4M FLASH USER MODE TABLE

C E

A9 A8 A6 A5 A1 A0 Ax/y DQ(0-7)

USER MODE

STANDBY

H X X X X X X X X X

HI-Z

READ

L H L A9 A8 A6 A5 A1 A0 Ax/y DQ

(0-7)

OUTPUT

DISABLE L H H X X X X X X X

HI-Z

READ

MANUFACTURE ID

L H L

VID

L/H L X L L X

MANUFACTURE

READ DEVICE ID

VID

L/H

DEVICE ID (T/B)

VERIFY SECTOR

PROTECTION

L H L

VID

X L X H L X

CODE

SECTOR

PROTECTION

L Pulse

VID

X L X X X X

VERIFY SECTOR

UNPROTECTION

L H L

VID

X H X H L X

CODE

SECTOR

UNPROTECTION

Pulse

VID

L X X H X X X

WRITE

L L H A9 A8 A6 A5 A1 A0 Ax/y DIN

(0-7)

NOTES:

1) L

, H = V

, V

= 11.0V

0.5V

2) X = Don’t care, either V

or V

3) Ax/y: Ax = Addr(x), Ay = Addr(y)

TABLE 4. DEVICE IDENTIFICTION

4M FLASH MANUFACTURER/DEVICE ID TABLE

A8 A6 A1 A0

DQ(7-0)

HEX

READ

MANUFACTURER ID

(1)

L L L

MANUFACTURER ID

READ

DEVICE ID

(2)

L L H

DEVICE ID

NOTES:

1) If a Manufacturing ID is read with A8 = L, the chip will output a configuration code 7Fh. A further

Manufacturing ID must be read with A8 = H.

2) If a Device ID is read with A8 = L, the chip will output a configuration code 7Fh. A further Device ID

must be read with A8 = H.

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EN29F040

Rev. D, Issue Date: 2001/07/05

USER MODE DEFINITIONS

Standby Mode

The EN29F040 has a CMOS-compatible standby mode, which reduces the

current to

1µA (typical).

It is placed in CMOS-compatible standby when the

pin is at V

0.5. The device also has a

TTL-compatible standby mode, which reduces the maximum V

current to < 1mA. It is placed in

TTL-compatible standby when the

pin is at V

. When in standby modes, the outputs are in a

high-impedance state independent of the

input.

Read Mode

The device is automatically set to reading array data after device power-up. No commands are

required to retrieve data. The device is also ready to read array data after completing an Embedded

Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode.

The system can read array data using the standard read timings, except that if it reads at an address

within erase-suspended sectors, the device outputs status data. After completing a programming

operation in the Erase Suspend mode, the system may once again read array data with the same

exception. See “Erase Suspend/Erase Resume Commands” for more information on this mode.

The system must issue the reset command to re-enable the device for reading array data if DQ5

goes high, or while in the autoselect mode. See “Reset Command” section.

See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more

information. The Read Operations table provides the read parameters, and Read Operation Timings

diagram shows the timing diagram.

Output Disable Mode

When the

pin is at a logic high level (V

), the output from the EN29F040 is disabled. The

output pins are placed in a high impedance state.

Auto Select Identification Mode

The autoselect mode provides manufacturer and device identification, and sector protection

verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for

programming equipment to automatically match a device to be programmed with its corresponding

programming algorithm. However, the autoselect codes can also be accessed in-system through the

command register.

When using programming equipment, the autoselect mode requires V

(10.5 V to 11.5 V) on

address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage

Method) table. In addition, when verifying sector protection, the sector address must appear on the

appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The

Command Definitions table shows the remaining address bits that are don’t care. When all

necessary bits have been set as required, the programming equipment may then read the

corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system; the host system can issue the autoselect command via

the command register, as shown in the Command Definitions table. This method does not require

. See “Command Definitions” for details on using the autoselect mode.

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EN29F040

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Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are

don’t care for this command.

The reset command may be written between the sequence cycles in an erase command sequence

before erasing begins. This resets the device to reading array data. Once erasure begins, however,

the device ignores reset commands until the operation is complete. The reset command may be

written between the sequence cycles in a program command sequence before programming begins.

This resets the device to reading array data (also applies to programming in Erase Suspend mode).

Once programming begins, however, the device ignores reset commands until the operation is

complete.

The reset command may be written between the sequence cycles in an autoselect command

sequence. Once in the autoselect mode, the reset command must be written to return to reading

array data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command returns the device

to reading array data (also applies during Erase Suspend).

Write Mode

Programming is a four-bus-cycle operation. The program command sequence is initiated by writing

two unlock write cycles, followed by the program set-up command. The program address and data

are written next, which in turn initiate the Embedded Program algorithm. The system is not required

to provide further controls or timings. The device automatically provides internally generated program

pulses and verifies the programmed cell margin. Table 5 (Command Definitions) shows the address

and data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data

and addresses are no longer latched. The system can determine the status of the program operation

by using DQ7 or DQ6. See “Write Operation Status” for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored.

Programming is allowed in any sequence and across sector boundaries. A bit cannot be

programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to

“1”, or cause the Data# Polling algorithm to indicate the operation was successful. However, a

succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.

COMMAND DEFINITIONS

The operations of the EN29F040 are selected by one or more commands written into the command

Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences

written at specific addresses via the command register. The sequences for the specified operation

are defined in the Command Table (Table 5). Incorrect addresses, incorrect data values or

improper sequences will reset the device to the read mode.

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EN29F040

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Table 5. EN29F040 Command Definitions

Write Cycle

Command

Sequence

Read/Reset

Write

Cycles

Req’d

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read

RA RD

Reset

1 XXXh

F0h

Read/Reset

4 555h

AAh

2AAh

55h

555h

F0h

AutoSelect

Manufacturer ID

4 555h

AAh

2AAh

55h

555h

90h

000h/

100h

7Fh/

1Ch

AutoSelect Device ID

4 555h

AAh

2AAh

55h

555h

90h

001h/

101h

7Fh/

04h

AutoSelect Sector

Protect Verify

4 555h

AAh

2AAh

55h

555h

90h

BA &

02h

00h/

01h

Byte Program

4 555h

AAh

2AAh

55h

555h

A0h

Chip Erase

555h AAh 2AAh 55h 555h 80h 555h AAh

2AAh 55h 555h 10h

Sector Erase

555h AAh 2AAh 55h 555h 80h 555h AAh

2AAh 55h BA 30h

Sector Erase Suspend

1 xxxh

B0h

Sector Erase Resume

1 xxxh

30h

Notes:

RA = Read Address: address of the memory location to be read.

This one is a read cycle.

RD = Read Data: data read from location RA during Read operation.

This one is a read cycle.

PA = Program Address: address of the memory location to be programmed

PD = Program Data: data to be programmed at location PA

BA = Sector Address: address of the Sector to be erased. Address bits A17-A13 uniquely select any Sector.

Byte Programming Command

Programming the EN29F040 is performed on a byte-by-byte basis using a four bus-cycle operation

(two unlock write cycles followed by the Program Setup command and Program Data Write cycle).

When the program command is executed, no additional CPU controls or timings are necessary. An

internal timer terminates the program operation automatically. Address is latched on the falling edge

W E

, whichever is last; data is latched on the rising edge of

W E

, whichever is first.

The program operation is completed when EN29F040 returns the equivalent data to the programmed

location.

Programming status may be checked by sampling data on DQ7 (

DATA

polling) or on DQ6 (toggle

bit). Changing data from 0 to 1 requires an erase operation. When programming time limit is

exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read mode.

Chip Erase Command

Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the

chip erase command, which in turn invokes the Embedded Erase algorithm. The device does

not require

the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and

verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required

to provide any controls or timings during these operations. The Command Definitions table shows the

address and data requirements for the chip erase command sequence.

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EN29F040

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Any commands written to the chip during the Embedded Erase algorithm are ignored.

The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write

Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete,

the device returns to reading array data and addresses are no longer latched.

Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in

“AC Characteristics” for parameters, and Chip/Sector Erase Operation Timings for timing waveforms.

Sector Erase Command

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two

un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by

the address of the sector to be erased, and the sector erase command. The Command Definitions table

shows the address and data requirements for the sector erase command sequence.

The device does

not require the system to preprogram the memory prior to erase. The Embedded Erase

algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical

erase. The system is not required to provide any controls or timings during these operations.

This device does not support multiple sector erase commands. Sector Erase operation will

commence immediately after the first 30h command is written. The first sector erase operation must

finish before another sector erase command can be given.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other

commands are ignored.

When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses

are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or

DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4 illustrates the

algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC

Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing

waveforms.

Erase Suspend / Resume Command

The Erase Suspend command allows the system to interrupt a sector erase operation and then read data

from, or program data to, any sector not selected for erasure. This command is valid only during the

sector erase operation. The Erase Suspend command is ignored if written during the chip erase operation

or Embedded Program algorithm. Addresses are “don’t-cares” when writing the Erase Suspend

command.

When the Erase Suspend command is written during a sector erase operation, the device requires a

maximum of 20 µs to suspend the erase operation.

After the erase operation has been suspended, the system can read array data from or program data to

any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.)

Normal read and write timings and command definitions apply. Reading at any address within erase-

suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2

together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status”

for information on these status bits.

After an erase-suspended program operation is complete, the system can once again read array data

within non-suspended sectors. The system can determine the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more

information.

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EN29F040

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The system must write the Erase Resume command (address bits are “don’t care”) to exit the

erase suspend mode and continue the sector erase operation. Further writes of the Resume command

are ignored. Another Erase Suspend command can be written after the device has resumed erasing.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The

hardware sector unprotection feature re-enables both program and erase operations in previously

protected sectors.

Sector protection/unprotection must be implemented using programming equipment. The procedure re-

quires a high voltage (V

) on address pin A9 and the control pins.

Contact Eon Silicon Devices, Inc. for

an additional supplement on this feature.

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EN29F040

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WRITE OPERATION STATUS

DQ7

DATA

Polling

The EN29F040 provides

DATA

Polling on DQ7 to indicate to the host system the status of the

embedded operations. The

DATA

Polling feature is active during the Byte Programming, Sector

Erase, Chip Erase, and Erase Suspend. (See Table 6)

When the Byte Programming is in progress, an attempt to read the device will produce the

complement of the data last written to DQ7. Upon the completion of the Byte Programming, an

attempt to read the device will produce the true data last written to DQ7. For the Byte Programming,

DATA

polling is valid after the rising edge of the fourth

C E

pulse in the four-cycle sequence.