M5M5V4R04J-12,-15
MITSUBISHI LSIs
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
1
1997.11.20 Rev.F
DESCRIPTION
The M5M5V4R04J is a family of 1048576-word by 4-bit static
RAMs, fabricated with the high performance CMOS silicon gate
process and designed for high speed application.
The M5M5V4R04J is offered in a 32-pin plastic small outline J-
lead package(SOJ).
These device operate on a single 3.3V supply, and are directly
TTL compatible. They include a power down feature as well.
COLUMN
ADDRESS
DECODERS
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
18 19 20 21 22
16
28 29
A
5
A
8
A
7
A
6
A
4
A
3
A
2
A
1
A
0
1
2
3
4
5
12
13
14
15
S
6
OE
27
W
11
DQ
4
DQ
3
DQ
2
DQ
1
7
10
23
26
COLUMN I/O CIRCUITS
COLUMN INPUT BUFFERS
ROW ADDRESS DECODERS
ROW INPUT BUFFERS
OUTPUT BUFFERS
DATA INPUT BUFFERS
VCC
24
GND
9
8
25
MEMORY ARRAY
512 ROWS
8192 COLUMNS
COLUMN ADDRESS
DECODERS
(3.3V)
(0V)
BLOCK DIAGRAM
address
inputs
address inputs
data
inputs/
outputs
Outline 32P0K(SOJ)
data inputs/
outputs
write control
input
chip select
input
output enable
input
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
3
A
2
A
1
A
0
DQ
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
W
A
16
A
10
A
11
OE
A
9
A
8
S
A
7
A
6
A
5
A
4
DQ
2
DQ
3
DQ
4
A
13
A
14
A
12
18
17
GND
GND
address
inputs
address
inputs
address
inputs
address
inputs
V
CC
V
CC
(0V)
(0V)
(3.3V)
(3.3V)
M5M5V4R04J
NC
A
15
A
18
A
19
A
17
data inputs/
outputs
data inputs/
outputs
data inputs/
outputs
A
17
30
A
18
31
A
19
32
FEATURES
• Fast access time
M5M5V4R04J-12
••••
12ns(max)
M5M5V4R04J-15
••••
15ns(max)
• Low power dissipation Active
••••••••••
297mW(typ)
Stand by
•••••••
3.3mW(typ)
• Single +3.3V power supply
• Fully static operation : No clocks, No refresh
• Common data I/O
• Easy memory expansion by S
• Three-state outputs : OR-tie capability
• OE prevents data contention in the I/O bus
• Directly TTL compatible : All inputs and outputs
APPLICATION
High-speed memory units
PACKAGE
32pin 400mil SOJ
M5M5V4R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
2
The operation mode of the M5M5V4R04J is determined by a
combination of the device control inputs S, W and OE. Each
mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps
with the low level S. The address must be set-up before the
write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W or
S, whichever occurs first, requiring the set-up and hold time
relative to these edge to be maintained. The output enable
input OE directly controls the output stage. Setting the OE at
a high level, the output stage is in a high impedance state,
and the data bus
contention problem in the write cycle is eliminated.
A read cycle is excuted by setting W at a high level and
OE at a low level while S are in an active state (S=L).
When setting S at high level, the chip is in a non-
selectable mode in which both reading and writing are
disable. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips and
memory expansion by S.
Signal-S controls the power-down feature. When S goes
high, power dissapation is reduced extremely. The access
time from S is equivalent to the address access time.
FUNCTION
FUNCTION TABLE
Icc
S
W
OE
H
Mode
Non selection
Stand by
ABSOLUTE MAXIMUM RATINGS
DQ
High-impedance
X
X
L
Write
Active
Din
L
X
L
Read
Active
Dout
H
L
L
Active
High-impedance
H
H
Operating temperature
V
cc
V
I
V
O
P
d
T
opr
T
stg
V
V
V
mW
-2.0 ~ 4.6
1000
0 ~ 70
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Storage temperature
(bias)
Symbol
Unit
Conditions
With respect to GND
Ratings
*
T
stg(bias)
Storage temperature
-10 ~ 85
V
IH
V
IL
V
OH
V
V
V
Vcc+0.3
0.8
2.0
2.4
V
OL
0.4
Symbol
Parameter
Max
Typ
Limits
Min
Condition
Unit
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
I
I
I
CC1
I
CC2
I
CC3
mA
mA
160
I
OZ
2
10
AC
DC
10
Input current
Active supply current
(TTL level)
Stand by current
(TTL level)
Output current in off-state
Stand by current
90
100
150
12ns cycle
V
15ns cycle
mA
75
AC
DC
50
70
12ns cycle
15ns cycle
1
-2.0 ~ VCC+0.5
*
-65 ~ 150
C
C
C
Ta=25 C
*Pulse width
≤
20ns, In case of DC:-0.5V
DC ELECTRICAL CHARACTERISTICS
+10%
-5%
(Ta=0 ~ 70 C, Vcc=3.3V unless otherwise noted)
-0.3
µ
A
µ
A
I
OH
=-4mA
I
OL
= 8mA
V
I
= 0~Vcc
V
I (S)
= V
IL
other inputs V
IH
or V
IL
Output-open(duty 100%)
V
I (S)
=
Vcc
≥
0.2V
other inputs V
I
≤
0.2V
or V
I
≥
Vcc-0.2V
V
I (S)
= V
IH
V
I (S)
= V
IH
V
O
= 0~Vcc
-2.0 ~ VCC+0.5
*
M5M5V4R04J-12,-15
MITSUBISHI LSIs
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
3
C
I
C
O
Input capacitance
Output capacitance
V
I
=GND, V
I
=25mVrms,f=1MHz
V
O
=GND, V
O
=25mVrms,f=1MHz
7
8
pF
pF
CAPACITANCE
Symbol
Parameter
Limit
Max
Typ
Min
Test Condition
Unit
AC ELECTRICAL CHARACTERISTICS
(1)MEASUREMENT CONDITION
+10%
-5%
(Ta=0 ~ 70 C, Vcc=3.3V unless otherwise noted)
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is Vcc=5V,Ta=25 C
3: C
I
,C
O
are periodically sampled and are not 100% tested.
+10%
-5%
(Ta=0 ~ 70 C, Vcc=3.3V unless otherwise noted)
Output timing reference levels V =1.5V, V =1.5V
Input pulse levels V =3.0V, V =0.0V
Input rise and fall time 3ns
Input timing reference levels V =1.5V, V =1.5V
Output loads
Fig1 ,Fig2
IH
IH
IL
IL
OH
OL
••••••••••••••••••••••••
••••••••••••••••••••••••••••••••••••••
••••••••••••
••••••••••
••••••••••••••••••••••••••••••••••••••••••
Vcc
DQ
Fig.2 Output load for t , t
en
dis
5pF
(including
scope and JIG)
Fig.1 Output load
480
Ω
255
Ω
RL=50
Ω
VL=1.5V
Z0=50
Ω
OUTPUT
M5M5V4R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
4
(2)READ CYCLE
Output disable time after W low
Parameter
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after S high
Output disable time after OE high
Output enable time after S low
Output enable time after OE low
Data valid time after address change
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
M5M5V4R04J -12
Limits
Max
Min
12
12
6
6
6
12
0
3
0
M5M5V4R04J -15
Max
Min
15
15
8
7
7
15
0
3
0
Power-up time after chip selection
Power-down time after chip selection
0
12
0
15
ns
ns
0
0
0
0
(3)WRITE CYCLE
Parameter
Write cycle time
Write pulse width
Address setup time(W)
Address to W High
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time after OE high
Output enable time after W high
Output enable time after OE low
10
0
10
12
6
6
0
0
Unit
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max
Min
Max
Min
6
0
1
12
0
0
12
15
7
7
0
0
7
0
1
ns
ns
ns
10
ns
12
0
0
0
0
Address setup time(S)
0
M5M5V4R04J -12
M5M5V4R04J -15
t
dis
(S)
t
dis
(OE)
t
en
(S)
t
en
(OE)
t
CR
t
a
(A)
t
a
(OE)
t
a
(S)
t
v
(A)
Symbol
t
PU
t
PD
t
CW
t
w
(W)
t
su
(A-WH)
t
su
(A)1
t
h
(D)
t
su
(D)
t
su
(S)
t
rec
t
dis
(W)
t
en
(W)
(OE)
t
en
t
dis
(OE)
Symbol
(W)
t
su
(A)2
M5M5V4R04J-12,-15
MITSUBISHI LSIs
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
5
(4)TIMING DIAGRAMS
A
0~19
Read cycle 1
t
CR
V
IH
V
IL
PREVIOUS DATA VALID
UNKNOWN
DATA VALID
V
OH
V
OL
DQ
1~4
W=H
S=L
OE=L
Read cycle 2
(Note 4)
S
W=H
OE=L
UNKNOWN
V
OH
V
OL
DQ
1~4
V
IH
V
IL
DATA VALID
t
PU
I
CC
1
I
CC
2
t
PD
50%
50%
(Note 5)
(Note 5)
Icc
t
CR
Read cycle 3
(Note 6)
OE
W=H
S=L
UNKNOWN
DATA VALID
V
OH
V
OL
DQ
1~4
V
IH
V
IL
(Note 5)
t
CR
(Note 5)
(A)
ta
(A)
tv
(A)
tv
ta
(S)
ten
(S)
t
dis
(S)
Note 4. Addresses valid prior to or coincident with S transition low.
5. Transition is measured
±
500mv from steady state voltage with specified loading in Figure 2.
ta
(OE)
ten
(OE)
t
dis
(OE)
Note 6. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
M5M5V4R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
6
Write cycle ( W control mode )
A
0~19
W
DQ
1~4
S
t
CW
OE
DQ
1~4
(Note7)
(Note7)
DATA STABLE
Hi-Z
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
Note 7: Hatching indicates the state is don't care.
8: When the falling edge of W is simultaneous or prior to the falling edge of S, the output is maintained in the high impedance.
9: t
en
,t
dis
are periodically sampled and are not 100% tested.
Write cycle (S control mode )
A
0~19
W
DQ
1~4
S
t
CW
DQ
1~4
DATA STABLE
(Note7)
(Note8)
Hi-Z
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
(Note7)
V
OH
V
OL
(W)
tsu
(S)
tsu
(A-WH)
(A)
tsu
t
w
(W)
trec
t
dis
(OE)
ten
(OE)
ten
(W)
t
dis
(W)
(Note 5)
(D)
tsu
(D)
th
(Note 5)
tw
(W)
trec
(W)
tsu
(S)
tsu
(A)
(D)
(D)
t
dis
(W)
(Note5)
(Note5)
tsu
th
ten
(S)
(Output Data)
(Input Data)
(Output Data)
(Input Data)