MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
Preliminary Spec.
MITSUBISHI
ELECTRIC
9/Nov. /1998
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0285-0.0
( / 23 )
Specifications subject to
change without notice.
DESCRIPTION
The MH8V725BAZTJ is 8388608-word x 72-bit dynamic
ram module. This consist of nine industry standard 8M x 8
dynamic RAMs in TSOP and three industry standard input
buffer in TSSOP.
The mounting of TSOP on a card edge dual in-line package
provides any application where high densities and large of
quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
MH8V725BAZTJ-5
Type name
/RAS
access
time
(max.ns)
/CAS
Address
/OE
Cycle
Power
access
time
(max.ns)
access
time
(max.ns)
access
time
(max.ns)
time
(min.ns)
dissipation
(typ.W)
50
18
30
18
20
90
110
Utilizes industry standard 8M x 8 RAMs in TSOP and industry
standard input buffer in TSSOP
168-pin (84-pin dual dual in-line package)
Single +3.3V(±0.3V) supply operation
Low stand-by power dissipation
116.2mW(Max) . . . . . . . . . . LVCMOS input level
Low operation power dissipation
MH8V725BAZTJ -5 . . . . . . . . . . . . . . . . . . 3.34W(Max)
MH8V725BAZTJ -6 . . . . . . . . . . . . . . . . . . 3.02W(Max)
All input are directly LVTTL compatible
All output are three-state and directly LVTTL compatible
Includes(0.22uF x 11) decoupling capacitors
4096 refresh cycle every 64ms (A0~12)
Hyper-page mode,Read-modify-write,
/CAS before /RAS refresh,Hidden refresh capabilities
JEDEC standard pin configuration & Buffered PD pin
Buffered input except /RAS and DQ
Gold plating contact pads
APPLICATION
Main memory unit for computers , Microcomputer memory
PD&ID TABLE
PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0
ID1
- 6
- 5
1 = NC , 0 = drive to VOL
PD pin . . . buffered. When /PDE is low, PD information can be read
ID pin . . . non-buffered
1
0
1
1
1
0
0
0
0
0
1
0
1
1
1
1
1
0
0
0
2.80
2.35
PIN CONFIGURATION
1pin
10pin
11pin
40pin
41pin
84pin
85pin
94pin
95pin
124pin
125pin
168pin
FRONT SIDE
BACK SIDE
60
20
35
MH8V725BAZTJ-6
1
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
Preliminary Spec.
MITSUBISHI
ELECTRIC
9/Nov. /1998
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0285-0.0
( / 23 )
Specifications subject to
change without notice.
PIN CONFIGURATION
Reserved: Reserved use
RFU: Reserved for future use
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
9
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
51
85
86
87
88
89
90
91
92
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
93
127
128
129
130
131
132
133
134
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
135
Reserved
Vss
DQ36
DQ37
DQ38
DQ39
Vcc
DQ40
DQ41
DQ42
DQ43
DQ44
Vss
DQ45
DQ46
DQ47
DQ48
DQ49
Vcc
DQ50
DQ51
DQ52
DQ53
Vss
Reserved
Reserved
Vcc
RFU
RFU
Vss
A1
A3
A5
A7
A9
Vcc
RFU
B0
Reserved
Reserved
Reserved
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
DQ16
DQ17
Vss
Reserved
Vcc
/WE0
/CAS0
/RAS0
/OE0
Vss
A0
A2
A4
A6
A8
A12
Vcc
RFU
RFU
DQ26
Vss
/OE2
/RAS2
/CAS4
Reserved
/WE2
Vcc
Reserved
Reserved
DQ18
DQ19
Vss
DQ20
DQ21
DQ22
DQ23
Vcc
DQ24
RFU
RFU
RFU
RFU
DQ25
DQ27
DQ30
Vss
DQ28
DQ29
DQ31
Vcc
DQ32
Vss
PD1
PD3
PD5
PD7
ID0
Vcc
DQ34
DQ33
DQ35
DQ62
Vss
RFU
Reserved
/PDE
Vcc
Reserved
Reserved
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
RFU
RFU
RFU
RFU
DQ61
DQ63
DQ66
Vss
DQ64
DQ65
DQ67
Vcc
DQ68
Vss
PD2
PD4
PD6
PD8
ID1
Vcc
DQ70
DQ69
DQ71
A10
A11
2
Reserved
Reserved
Reserved
Reserved
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
Preliminary Spec.
MITSUBISHI
ELECTRIC
9/Nov. /1998
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0285-0.0
( / 23 )
Specifications subject to
change without notice.
BLOCK DIAGRAM
A0
B0
A1~A12
D0~D4
D5~D8
D0~D8
. . .
Vcc
Vss
C
1
~C
11
D0~D8
& INPUT BUFFER
ROW ADDRESS STROBE INPUT
COLUMN ADDRESS STROBE INPUT
WRITE CONTROL INPUT
OUTPUT ENABLE INPUT
DATA I/O
ADDRESS INPUT
POWER SUPPLY
GROUND
/RAS
/CAS
/WE
/OE
A, B
DQ
Vcc
Vss
PIN NAME
FUNCTION
DQ32
DQ33
DQ34
DQ35
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
/RAS0
/CAS0
/WE0
/OE0
/RAS
/CAS
/W
/OE
DQ1
~DQ8
D0
DQ68
DQ69
DQ70
DQ71
DQ64
DQ65
DQ66
DQ67
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DQ36
DQ37
DQ38
DQ39
/RAS2
/CAS4
/WE2
/OE2
D : M5M465805BTP
/RAS
/CAS
/W
/OE
DQ1
~DQ8
D1
/RAS
/CAS
/W
/OE
DQ1
~DQ8
D2
/RAS
/CAS
/W
/OE
DQ1
~DQ8
D3
/RAS
/CAS
/W
/OE
DQ1
~DQ8
D4
/RAS
/CAS
/W
/OE
DQ1
~DQ8
D5
/RAS
/CAS
/W
/OE
DQ1
~DQ8
D6
/RAS
/CAS
/W
/OE
DQ1
~DQ8
D7
/RAS
/CAS
/W
/OE
DQ1
~DQ8
D8
3
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
Preliminary Spec.
MITSUBISHI
ELECTRIC
9/Nov. /1998
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0285-0.0
( / 23 )
Specifications subject to
change without notice.
FUNCTION
The MH8V725BAZTJ provide, in addition to normal read,
write, and read-modify-write operations,
a number of other functions, e.g., Hyper page mode, /CAS
before /RAS refresh, and delayed-write. The input conditions
for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
/RAS
/CAS
Inputs
Input/Output
Refresh
Remark
/W
Row
address
address
Column
Output
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
/CAS before /RAS refresh
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
DNC
NAC
APD
APD
APD
APD
DNC
DNC
OPN
VLD
IVD
VLD
VLD
OPN
NO
NO
NO
NO
YES
YES
Hyper page mode
identical
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
/OE
ACT
DNC
DNC
ACT
ACT
DNC
APD
APD
APD
APD
DNC
DNC
Input
VLD
VLD
VLD
OPN
DNC
OPN
4
Standby
NAC
DNC
DNC
DNC
OPN
NO
DNC
DNC
DNC
Hidden refresh
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
Preliminary Spec.
MITSUBISHI
ELECTRIC
9/Nov. /1998
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0285-0.0
( / 23 )
Specifications subject to
change without notice.
(Ta = 0~70°C, Vcc = 3.3V±0.3V, Vss = 0V, unless otherwise noted)
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted) (Note 2)
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
IO
Pd
Topr
Tstg
Parameter
Conditions
Ratings
-0.5~ 4.6
50
10.7
0~70
-40~100
With respect to Vss
Ta=25°C
Supply voltage
Output current
Power dissipation
Operating temperature
Storage temperature
RECOMMENDED OPERATING CONDITIONS
Unit
Limits
Min
Nom
Max
V
V
V
V
3.6
0
Vcc+0.3
0.8
3.3
0
3.0
0
2.0
-0.3
Parameter
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage
Vcc
Symbol
Vss
VIH
VIL
(Ta=0~70°C, unless otherwise noted) (Note 1)
ELECTRICAL CHARACTERISTICS
CAPACITANCE
Symbol
VOH
VOL
IOZ
I I
ICC1 (AV)
ICC2
ICC4(AV)
ICC6(AV)
High-level output voltage
Parameter
Limits
Min
Max
Unit
Typ
Test conditions
Low-level output voltage
Off-state output current
Input current (except /RAS)
Average supply
current
from Vcc operating
(Note 3,4,5)
(Note 3,4,5)
(Note 3,5)
Supply current from Vcc , stand-by
Average supply current
from Vcc
Hyper-Page-Mode
Average supply current from
Vcc
/CAS before /RAS refresh
mode
IOH=-2.0mA
IOL=2.0mA
Q floating 0V
≤
VOUT
≤
Vcc
0V
≤
VIN
≤
Vcc+0.3, Other input pins=0V
/RAS, /CAS cycling
tRC=tWC=min.
output open
/RAS=/CAS =VIH, output open
/RAS=/CAS=WE
≥
Vcc -0.2, output open
/RAS=VIL,/CAS cycling
tPC=min.
output open
/CAS before /RAS refresh cycling
tRC=min.
output open
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Column address can be changed once or less while /RAS=VIL and /CAS=VIH
I I (RAS)
Input current (/RAS)
0V
≤
VIN
≤
Vcc+0.3, Other input pins=0V
2.4
0
-10
-10
-90
Vcc
0.4
10
10
90
V
V
uA
mA
mA
mA
mA
Limits
Min
Max
Unit
Typ
pF
pF
pF
CI
CI (/RAS)
C(DQ)
Symbol
Parameter
Test conditions
Input capacitance, /RAS input
Input/Output capacitance,DATA
VI=Vss
f=1MHZ
Vi=25mVrms
Input capacitance, except /RAS input
20
45
22
Unit
V
mA
W
°C
°C
- 5
- 6
- 6
920
830
830
1100
29
24.5
Note 1 : All voltage values are with respect to Vss
uA
uA
5
- 6
- 5
920
- 5
1190
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
Preliminary Spec.
MITSUBISHI
ELECTRIC
9/Nov. /1998
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0285-0.0
( / 23 )
Specifications subject to
change without notice.
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)
SWITCHING CHARACTERISTICS
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing /CAS before /RAS refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods
(greater than 64 ms) of /RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 1 TTL load and 100pF,VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=-2mA).
The reference levels for measuring of output signals are 2.0V(VOH)and 0.8V(VOL).
8: Assumes that tRCD
≥
tRCD(max), tASC
≥
tASC(max) and tCP
≥
tCP(max).
9: Assumes that tRCD
≤
tRCD(max) and tRAD
≤
tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD
≥
tRAD(max) and tASC
≤
tASC(max).
11: Assumes that tCP
≤
tCP(max) and tASC
≥
tASC(max).
12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT
≤
I ± 10uA I )
and is not reference to VOH(min) or VOL(max).
13: Output is disabled after both /RAS and /CAS go to high.
Limits
Parameter
Symbol
Unit
- 5
Min
Max
- 6
Min
Max
tCAC
tRAC
tAA
tCPA
tOEA
tOHR
tCLZ
Access time from /CAS
Access time from /RAS
Column address access time
Access time from /CAS precharge
Output hold time from /RAS
Output low impedance time /CAS low
Access time from /OE
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
(Note 13)
(Note 7)
ns
ns
ns
ns
ns
ns
ns
ns
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 14,15)
Limits
Min
Max
Parameter
Symbol
Unit
(Note16)
(Note17)
(Note18)
64
32
20
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Hyper-Page Mode Cycles)
Note 14: The timing requirements are assumed tT =2ns.
15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA. .
17: tRAD(max) is specified as a reference point only. If tRAD
≥
tRAD(max) and tASC
≤
tASC(max), access time is controlled exclusively by tAA.
18: tASC(max) is specified as a reference point only. If tRCD
≥
tRCD(max) and tASC
≥
tASC(max), access time is controlled exclusively by tCAC.
19: Either tDZC or tDZO must be satisfied.
20: Either tRDD or tCDD or tODD must be satisfied.
21: tT is measured between VIH(min) and VIL(max).
(Note19)
(Note20)
(Note19)
(Note20)
-5
Min
Max
64
40
25
-6
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tCDD
tODD
Refresh cycle time
/RAS high pulse width
Delay time, /RAS low to /CAS low
Delay time, /CAS high to /RAS low
Delay time, /RAS high to /CAS low
/CAS high pulse width
Column address delay time from /RAS low
Row address setup time before /RAS low
Column address setup time before /CAS low
Row address hold time after /RAS low
Column address hold time after /CAS low
Delay time, data to /CAS low
Delay time, data to /OE low
Delay time, /CAS high to data
Delay time, /OE high to data
-5
30
9
10
8
5
3
8
5
0
-5
-5
18
18
-5
40
9
10
10
7
5
10
5
0
-5
-5
20
20
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
18
30
33
50
18
20
35
38
60
20
tOHC
Output hold time from /CAS
10
10
5
5
10
10
10
13
6
tOEZ
tOFF
tREZ